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參數(shù)資料
| 型號： | SAB9083H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 畫面疊加 |
| 英文描述： | Circular Connector; No. of Contacts:37; Series:JT02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:14-35 |
| 中文描述： | PICTURE-IN-PICTURE IC, PQFP100 |
| 封裝： | 14 X 20 X 2.80 MM, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 104K |
| 代理商： | SAB9083H |
1999 Nov 12
13
Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP)
controller
SAB9083
HBW
IDTH AND
VBW
IDTH
Bits HBWidth<2:0> and VBWidth<2:0>control the
horizontal and vertical border sizes in steps of two pixels
and one line. The default horizontal border size is four
pixels and the vertical border size is two lines per field.
Default means after power-up and no I
2
C-bus data sent to
the PIP controller.
In MP6 mode, the minimum value of HBWidth is two.
N
OTES
1.
Whentheinput signals forthemainand/or subchannel
are non-interlaced, joint line errors can occur. When
non-interlaced signals are input, the SAB9083
switches automatically to the non-interlaced mode.
When the prevent joint line error algorithm is switched
off (AlgOff is set to logic 1), joint line errors can still
occur in the 2-Field mode.
When a PAL signal is applied to the main channel and
an NTSC signal is applied to the subchannel, the
subchannel will automatically enter the 1-Field mode.
Now, a joint line error can occur. In the PAL/NTSC
mode, the subpicture will be smaller than the main
picture (difference of approximately 40 lines).
When an NTSC signal is applied to the main channel
and a PAL signal is applied to the subchannel, the
subchannel will automatically enter the 1-Field mode.
Now, a joint line error can occur. In the NTSC/PAL
mode, the subpicture will be larger than the main
picture (difference of approximately 40 lines):
ThemultistandardPIPmodesarenotmeantformixing
PAL and NTSC PIPs.
In all MP6 modes, the live PIP is displayed in the
1-Field mode when the input signal is PAL. This
means that joint line errors can occur in the live PIP
when the input signal is PAL.
Mixed NTSC/PAL multistandard PIP modes are
available by setting bit SNTSC to logic 1 when the
mainpictureisNTSCand thesubpictureisPAL.In this
way, the subchannel is forced to operate in NTSC
mode and the lower parts of the original PAL
subchannel PIPs (approximately 40 lines) will not be
displayed. The picture can be centred by changing the
value of the SAVfp bits.
2.
3.
4.
5.
6.
7.
8.
Mixed PAL/NTSC multistandard PIP modes are
available by setting bit DNTSC to logic 1 when the
mainpictureisPALandthesubpicture isNTSC.In this
way, the display channel is forced to operate in NTSC
mode and the lower parts of the original PAL main
picture (approximately 40 lines) will not be displayed.
Because the screen will not be filled completely in the
vertical direction, the use of a black background is
suggested here. The picture can be centred by
changing the value of the SAVfp bits.
Acquisition channel ADCs and clamping
The analog input signals are converted to digital signals by
three ADCs per channel. The resolution of the ADCs is
8 bits (DNL is 7 bits and INL is 6 bits) and the sampling is
performed at the system clock frequency of 28 MHz for the
Y input. A bias voltage (V
bias
) is used to decouple the AC
components on internal references.
The inputs should be AC coupled and an internal clamp
circuit (using external clamp capacitors) will clamp the
input to a level derived internally from V
ref(B)(MA/SA)
for the
luminance channels and, forthe chrominance channels, to
(V
ref(T)(MA/SA)
+ V
ref(B)(MA/SA)
)/2 + LSB/2. The clamping
starts at the active edge of the burst key. Internal video
buffers amplify the standard Y, U and V input signals to
the correct ADC levels.
PLL
The PLL generates an internal system clock of
1792
×
f
HSYNC
, from f
HSYNC
, which is approximately
28 MHz.
DACs and video buffers
The 28 MHz digital video signals are fed to the 8-bit DACs
that produce the required analog video signals. The video
buffers amplify these signals prior to being fed to the
output to drive another device.
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