參數(shù)資料
型號: SAF-C161S-L25M AA
廠商: Infineon Technologies
文件頁數(shù): 64/75頁
文件大?。?/td> 0K
描述: IC MCU 16BIT ROM/LESS MQFP-80-7
標(biāo)準(zhǔn)包裝: 1
系列: C16xx
核心處理器: C166
芯體尺寸: 16-位
速度: 25MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 63
程序存儲器類型: ROMless
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-QFP
包裝: 剪切帶 (CT)
產(chǎn)品目錄頁面: 736 (CN2011-ZH PDF)
其它名稱: SAF-C161S-L25MAACT
SAF-C161S-L25MAACT-ND
SAF-C161S-L25MAAINCT
C161S
Timing Characteristics
Data Sheet
63
V1.0, 2003-11
Table 19
Demultiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
t
A + tC + tF (100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
Unit
Min.
Max.
Min.
Max.
ALE high time
t
5
CC 11 +
t
A
TCL - 14
+
t
A
ns
Address setup to ALE
t
6
CC 5 +
t
A
TCL - 20
+
t
A
ns
ALE falling edge to RD,
WR (with RW-delay)
t
8
CC 15 +
t
A
TCL - 10
+
t
A
ns
ALE falling edge to RD,
WR (no RW-delay)
t
9
CC -10 +
t
A
-10
+
t
A
ns
RD, WR low time
(with RW-delay)
t
12
CC 34 +
t
C
2TCL - 16
+
t
C
ns
RD, WR low time
(no RW-delay)
t
13
CC 59 +
t
C
3TCL - 16
+
t
C
ns
RD to valid data in
(with RW-delay)
t
14
SR –
22 +
t
C
2TCL - 28
+
t
C
ns
RD to valid data in
(no RW-delay)
t
15
SR –
47 +
t
C
3TCL - 28
+
t
C
ns
ALE low to valid data in
t
16
SR –
45 +
t
A + tC
3TCL - 30
+
t
A + tC
ns
Address to valid data in
t
17
SR –
57 +
2
t
A + tC
4TCL - 43
+ 2
t
A + tC
ns
Data hold after RD
rising edge
t
18
SR 0
0
ns
Data float after RD rising
edge (with RW-delay
1))
t
20
SR –
36 +
2
t
A + tF
2TCL - 14
+ 22
t
A
+
t
F
ns
Data float after RD rising
edge (no RW-delay
t
21
SR –
15 +
2
t
A + tF
TCL - 10
+ 22
t
A
+
t
F
ns
Data valid to WR
t
22
CC 24 +
t
C
2TCL - 26
+
t
C
ns
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