參數(shù)資料
型號(hào): SAF-XC2285M-72F80LAA
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PQFP144
封裝: 0.50 mm pitch, GREEN, PLASTIC, LQFP-144
文件頁數(shù): 30/142頁
文件大?。?/td> 1112K
代理商: SAF-XC2285M-72F80LAA
XC2287M, XC2286M, XC2285M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Data Sheet
125
V2.0, 2009-03
Bus Cycle Control with the READY Input
The duration of an external bus cycle can be controlled by the external circuit using the
READY input signal. The polarity of this input signal can be selected.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
An asynchronous READY signal puts no timing constraints on the input signal but incurs
a minimum of one waitstate due to the additional synchronization stage. The minimum
duration of an asynchronous READY signal for safe synchronization is one CLKOUT
period plus the input setup time.
An active READY signal can be deactivated in response to the trailing (rising) edge of
the corresponding command (RD or WR).
If the next bus cycle is controlled by READY, an active READY signal must be disabled
before the first valid sample point in the next bus cycle. This sample point depends on
the programmed phases of the next cycle.
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