參數(shù)資料
型號(hào): SAF-XC2388C-200F100L
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-144
文件頁數(shù): 106/147頁
文件大?。?/td> 1798K
代理商: SAF-XC2388C-200F100L
XC2387C, XC2388C
XC2000 Family Derivatives / High Line
Functional Description
Data Sheet
61
V1.2, 2010-09
to a dedicated vector table location). The occurrence of a hardware trap is also indicated
by a single bit in the trap flag register (TFR). Unless another higher-priority trap service
is in progress, a hardware trap will interrupt any ongoing program execution. In turn,
hardware trap services can normally not be interrupted by standard or PEC interrupts.
Depending on the package option up to 3 External Service Request (ESR) pins are
provided. The ESR unit processes their input values and allows to implement user
controlled trap functions (System Requests SR0 and SR1). In this way reset, wakeup
and power control can be efficiently realized.
Software interrupts are supported by the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number. Alternatively to emulate an interrupt by software a
program can trigger interrupt requests by writing the Interrupt Request (IR) bit of an
interrupt control register.
3.7
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system built into the XC238xC provides a broad range of
debug and emulation features. User software running on the XC238xC can be debugged
within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface. This
either consists of the 2-pin Device Access Port (DAP) or of the JTAG port conforming to
IEEE-1149. The debug interface can be completed with an optional break interface.
The debugger controls the OCDS with a set of dedicated registers accessible via the
debug interface (DAP or JTAG). In addition the OCDS system can be controlled by the
CPU, e.g. by a monitor program. An injection interface allows the execution of OCDS-
generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported, as is the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing of data can be obtained via the debug interface, or via the external bus interface
for increased performance.
Tracing of program execution is supported by the XC2000 Family emulation device. With
this device the DAP can operate on clock rates of up to 20 MHz.
The DAP interface uses two interface signals, the JTAG interface uses four interface
signals, to communicate with external circuitry. The debug interface can be amended
with two optional break lines.
相關(guān)PDF資料
PDF描述
SAF-XC2388C-200F80L 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
SAK-XC2388C-200F80L 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
SAF-XC2388C-104F100L 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
SAH-XC2388C-200F80L 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
SAK-XC2388C-104F80L 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
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