
C165UTAH
Asynchronous/Synchr. Serial Interface
Data Sheet
276
2001-02-23
the two fixed dividers a fractional divider prescaler unit is available which allows to select
prescaler divider ratios of n/512 with n=0-511. Therefore, the baudrate of ASC is
determined by the module clock, the content of S0FDV, the reload value of S0BG and
the operating mode (asynchronous or synchronous).
Register S0BG is the dual-function Baudrate Generator/Reload register. Reading BG
returns the content of the timer BR_VALUE (bits 15...13 return zero), while writing to
S0BG always updates the reload register (bits 15...13 are insiginificant).
An auto-reload of the timer with the content of the reload register is performed each time
CON_BG is written to. However, if CON_R=’0’ at the time the write operation to BG is
performed, the timer will not be reloaded until the first instruction cycle after CON_R=’1’.
For a clean baudrate initialization S0BG should only be written if CON_R=’0’. If S0BG is
written with CON_R=’1’, an unpredicted behaviour of the ASC may occur during running
transmit or receive operations.
12.1.7.1
Baudrates in Asynchronous Mode
For asynchronous operation, the baudrate generator provides a clock f
BRT
with 16 times
the rate of the established baudrate. Every received bit is sampled at the 7th, 8th and 9th
cycle of this clock. The clock divider circuitry, which generates the input clock for the 13-
bit baudrate timer, is extended by a fracxtional divider circuitry, which allows the
adjustment of more accurate baudrates and the extension of the baudrate range.
The baudrate of the baudrate generator depends on the following input clock, bits and
register values :
– Input clock f
MOD
– Selection of the baudrate timer input clock f
DIV
by bits CON_FDE and CON_BRS
– If bit CON_FDE=1 (fractional divider) : value of register CON_FDV
– value of the 13-bit reload register S0BG
The output clock of the baudrate timer with the reload register is the sample clock in the
asynchronous modes of the ASC. For baudrate calculations, this baudrate clock f
BR
is
derived from the sample clock f
DIV
by a division by 16.