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參數(shù)資料
| 型號： | SAFC509-L |
| 廠商： | SIEMENS AG |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數(shù)： | 43/74頁 |
| 文件大?。?/td> | 1607K |
| 代理商： | SAFC509-L |
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C509-L
Semiconductor Group
42
The block diagram in
figure 18
shows the general configuration of the CCU. All CC1 to CC4
registers and the CRC register are exclusively assigned to timer 2. Each of the eight compare
registers CM0 through CM7 can either be assigned to timer 2 or to the faster compare timer, e.g. to
provide up to 8 PWM output channels. The assignment of the CMx registers - which can be done
individually for every single register - is combined with an automatic selection of one of the two
possible compare modes. The compare/capture registers CC10 to CC17 and the reload register
CT1REL are assigned to compare timer 1 and are mapped to the corresponding registers of the
compare timer.
The compare function and the reaction of the corresponding outputs depend on the timer/compare
register combination.
Table 7
shows the possible configurations of the CCU and the corresponding
compare modes which can be selected. The following sections describe the function of these
configurations.
Table 7
CCU Configurations
Assigned
Timer
Compare
Register
Compare Output at
Possible Modes
Timer 2
CRCH/CRCL
CCH1/CCL1
CCH2/CCL2
CCH3/CCL3
CCH4/CCL4
P1.0/INT3/CC0
P1.1/INT4/CC1
P1.2/INT5/CC2
P1.3/INT6/CC3
P1.4/INT2/CC4
Compare mode 0, 1 + Reload
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture)
CCH4/CCL4
P1.4/INT2/CC4
P5.0/CCM0
to
P5.7/CCM7
Compare mode 1
“Concurrent compare“
CMH0/CML0
to
CMH7/CML7
P4.0/CM0
to
P4.7/CM7
Compare mode 0
COMSET
COMCLR
P5.0/CCM0
to
P5.7/CCM7
Compare mode 2
Compare
Timer
CMH0/CML0
to
CMH7/CML7
P4.0/CM0
to
P4.7/CM7
Compare mode 1
Compare
Timer 1
CC1H0/CC1L0
to
CC1H7/CC1L7
P5.0/CCM0
to
P5.7/CCM7
Compare mode 0 / capture
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