參數(shù)資料
型號(hào)： SAH-XC2210U-8F66R
廠商： INFINEON TECHNOLOGIES AG
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PDSO38
封裝： 0.50 MM PITCH, GREEN, PLASTIC, TSSOP-38
文件頁(yè)數(shù)： 30/103頁(yè)
文件大小： 2957K
代理商： SAH-XC2210U-8F66R
XC2210U
XC2000 Family / Compact Line
Functional Description
PRELIMINARY
Data Sheet
28
V1.0, 2010-12
to a dedicated vector table location). The occurrence of a hardware trap is also indicated
by a single bit in the trap flag register (TFR). Unless another higher-priority trap service
is in progress, a hardware trap will interrupt any ongoing program execution. In turn,
hardware trap services can normally not be interrupted by standard or PEC interrupts.
Depending on the package option up to 3 External Service Request (ESR) pins are
provided. The ESR unit processes their input values and allows to implement user
controlled trap functions (System Requests SR0 and SR1). In this way reset, wakeup
and power control can be efficiently realized.
Software interrupts are supported by the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number. Alternatively to emulate an interrupt by software a
program can trigger interrupt requests by writing the Interrupt Request (IR) bit of an
interrupt control register.
3.6
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system built into the XC2210U provides a broad range of
debug and emulation features. User software running on the XC2210U can be debugged
within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface. This
consists of the 2-pin Device Access Port (DAP) or of the 1-pin Single Pin DAP (SPD) or
of the JTAG port conforming to IEEE-1149. The debug interface can be completed with
an optional break interface.
The debugger controls the OCDS with a set of dedicated registers accessible via the
debug interface (SPD, DAP or JTAG). In addition the OCDS system can be controlled
by the CPU, e.g. by a monitor program. An injection interface allows the execution of
OCDS-generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported, as is the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing of data can be obtained via the debug interface, or via the external bus interface
for increased performance.
Tracing of program execution is supported by the XC2000 Family emulation device.
The SPD interface uses one interface signal, DAP interface uses two interface signals,
the JTAG interface uses four interface signals, to communicate with external circuitry.
The debug interface can be amended with two optional break lines.
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