參數(shù)資料
型號: SAH-XC2388C-200F80L
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-144
文件頁數(shù): 43/147頁
文件大?。?/td> 1798K
代理商: SAH-XC2388C-200F80L
XC2387C, XC2388C
XC2000 Family Derivatives / High Line
Electrical Parameters
Data Sheet
137
V1.2, 2010-09
4.7.8
Debug Interface Timing
The debugger can communicate with the XC238xC either via the 2-pin DAP interface or
via the standard JTAG interface.
Debug via DAP
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 39 is valid under the following conditions:
C
L= 20 pF; voltage_range= upper
Table 39
DAP Interface Timing for Upper Voltage Range
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
DAP0 clock period
1)
1) See the DAP chapter for clock rate restrictions in the Active::IDLE protocol state.
t
11 SR
25
ns
DAP0 high time
t
12 SR
8
ns
DAP0 low time
t
13 SR
8
ns
DAP0 clock rise time
t
14 SR
4ns
DAP0 clock fall time
t
15 SR
4ns
DAP1 setup to DAP0
rising edge
t
16 SR
3
ns
pad_type= high
speed
2)
2) Available high speed pins can be found in the pin definitions table in chapter 2.
6
ns
pad_type= stan
dard
DAP1 hold after DAP0
rising edge
t
17 SR
4
ns
pad_type= high
speed
6
ns
pad_type= stan
dard
DAP1 valid per DAP0
clock period
3)
3) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t
19 CC
19
21
ns
pad_type= high
speed
17
20
ns
pad_type= stan
dard
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