參數(shù)資料
型號: SAK-XC167CI-16F20F
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller with C166SV2 Core
中文描述: 16位單片機與C166SV2核心
文件頁數(shù): 23/89頁
文件大?。?/td> 803K
代理商: SAK-XC167CI-16F20F
XC167-16
Derivatives
Functional Description
Data Sheet
21
V1.2, 2006-03
3
Functional Description
The architecture of the XC167 combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external
resources (see
Figure 3
).
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC167.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC167.
Figure 3
Block Diagram
Interrupt Bus
XTAL
MCB04323_x7.vsd
Osc / PLL
Clock Generation
RTC
WDT
GPT
T2
T3
T4
T5
T6
SSC0
(SPI)
BRGen
ASC1
(USART)
BRGen
ADC
8/10-Bit
16
Channels
CC2
T7
T8
EBC
XBUS Control
External Bus
Control
ProgMem
Flash
128 KBytes
P 20
4
16
Port 5
16
PSRAM
DPRAM
DSRAM
C166SV2-Core
P
D
CPU
ASC0
(USART)
BRGen
IIC
BRGen
SSC1
(SPI)
BRGen
CC1
T0
T1
Twin
CAN
A
B
PORT1
PORT0
Port 2
Port 3
Port 4
Port 6
P 7
Port 9
16
8
15
8
8
6
6
Interrupt & PEC
Peripheral Data Bus
OCDS
Debug Support
CC6
T12
T13
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SAKXC167CI16F40FBB 制造商:Infineon Technologies AG 功能描述:
SAK-XC167CI-16F40FBB 制造商:Infineon Technologies AG 功能描述: