參數(shù)資料
型號: SC14402CVJG
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 無繩電話/電話
英文描述: Complete Baseband Processor for DECT Handsets
中文描述: TELECOM, CORDLESS, BASEBAND CIRCUIT, PQFP100
封裝: LQFP-100
文件頁數(shù): 6/7頁
文件大?。?/td> 78K
代理商: SC14402CVJG
Copyright 1998 National Semiconductor Corp.
6
www.national.com
NOTE: All digital outputs can sink/source 2 mA unless
otherwise specified. All digital inputs are Schmitt trig-
ger types. After reset all I/Os are set to input and all
pull-up or pull-down resistors are enabled. The p0[1]
will be pulled down at start-up.
ACSn
70
5
OUTPUT. Auxiliary Chip Select not. This signal becomes low if the address range
is within the programmed address range.
OUTPUT. ADdress bit 3 to 0. In the HOLD mode these pins are input.
INPUT/OUTPUT (Slope controlled) Data bus bit 7..0
OUTPUT. ROM Chip Select not output. Low active if none of the internal peripher-
als or the ACSn is addressed.
OUTPUT. Address bit 10. In the HOLD mode these pins are input.
OUTPUT. Active low read. In the HOLD mode this pin is input.
OUTPUT. Address bit 11. In the HOLD mode these pins are input.
OUTPUT. Address bit 9. In the HOLD mode these pins are input.
OUTPUT. Address bit 8. In the HOLD mode these pins are input.
OUTPUT. Address bit 13. In the HOLD mode these pins are input
OUTPUT. Address bit 14. In the HOLD mode these pins are input.
OUTPUT. Masked Interrupt output (HOLD mode only) or Address bit 17.
OUTPUT. Active low write signal. In the HOLD mode this pin is input.
OUTPUT. Address bit 16,15 & 12. In the HOLD mode these pins are input.
OUTPUT. Address bit 7 to 4. In the HOLD mode these pins are input.
OUTPUT. Fixed bit clock output (1.152Mhz). Synchronized to the DECT bit clock.
Will be logic ‘0’ if the DECT Dedicated Instruction Processor (DiP) is frozen or
reset.
AD3..0
DAB7..0
RCSn
71-74
82-75
83
1b
1b
5b
AD10
RDn
AD11
AD9
AD8
AD13
AD14
MI/AD17
WRn
AD16,15, 12
AD7-4
CLKOUT
84
85
86
87
88
89
90
91
92
1b
1b
1b
1b
1b
1b
1b
5b
1b
1b
1b
1b
93-95
96-99
100
Table 1:
Pin Description
PIN NAME
TYPE
DESCRIPTION
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