參數(shù)資料
型號(hào): SC14404BFLBG
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 無(wú)繩電話/電話
英文描述: Complete Baseband Processor for DECT Handsets
中文描述: TELECOM, CORDLESS, BASEBAND CIRCUIT, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 3/6頁(yè)
文件大小: 175K
代理商: SC14404BFLBG
Copyright 2000 National Semiconductor Corp.
3
www.national.com
S
Order Number SC14404BFLBC (320kbyte Full FLASH, Boot mode B, 100 pins CSP
Order Number SC14404BxxBC (320kbyte ROM FLASH, Boot mode B, 100 pins CSP
Note 1:
All digital outputs can sink/source 2 mA unless otherwise specified. All digital inputs are Schmitt trigger types. After reset all I/Os are set to input
and all pull-up or pull-down resistors are enabled unless otherwise specified.
PU = Pull-up resistor enabled, PD = Pull-down resistor enabled, I = input
A-I, B-I = In Boot mode A or B input and pull-up or pull-down resistor disabled,
A-PD, B-PU = In Boot mode A, Pull-down resistor enabled. In Boot mode B, pull-up resistor enabled.
Note 2:
Reset state of address and data bus and WRn, RDn pins:
If SC14404: Hi-Z/1 means Hi-Z if RSTn is LOW, if RSTn goes HIGH it takes 32 SCLK cycles = 25 usec before these pin drives a ‘1’.
Table 1:
TQFP pin mapping onto CSP package (See table 2 for TQFP pin description)
1
2
3
4
5
6
7
8
9
10
A
1
99
96
93
89
88
86
85
83
76
B
8
2
98
95
92
90
87
80
77
74
C
10
5
3
97
94
84
82
78
73
71
D
11
12
7
6
100
79
81
72
70
68
E
13
15
9
4
16
91
75
69
67
64
F
14
17
19
25
41
66
54
59
65
63
G
18
20
22
31
29
50
56
57
62
61
H
21
23
28
32
34
44
47
53
55
60
J
24
27
30
37
40
42
45
48
52
58
K
26
33
35
36
38
39
43
46
49
51
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
SC14404 CSP pin diagram
(TOP View)
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