參數(shù)資料
型號(hào)： SC16C650A
廠商： NXP Semiconductors N.V.
英文描述： Universal Asynchronous Receiver/Transmitter (UART) with 32-byte FIFO and infrared (IrDA) encoder/decoder
中文描述： 通用異步接收器/發(fā)送器（UART）與32字節(jié)的FIFO和紅外（IrDA）編碼器/解碼器
文件頁(yè)數(shù)： 10/50頁(yè)
文件大小： 642K
代理商： SC16C650A
Philips Semiconductors
SC16C650A
UART with 32-byte FIFO and IrDA encoder/decoder
Product data
Rev. 04 — 20 June 2003
10 of 50
9397 750 11622
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.1 Internal registers
The SC16C650A provides 15 internal registers for monitoring and control. These
registers are shown in
Table 3
. Twelve registers are similar to those already available
in the standard 16C550. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),
and a user accessible scratchpad register (SPR). Beyond the general 16C550
features and capabilities, the SC16C650A offers an enhanced feature register set
(EFR, Xon/Xoff1-2) that provides on-board hardware/software flow control. Register
functions are more fully described in the following paragraphs.
[1]
[2]
[3]
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to “BF”
(HEX).
6.2 FIFO operation
The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger
level, but not the transmit trigger level. The SC16C650A provides independent trigger
levels for both receiver and transmitter. To remain compatible with SC16C550, the
transmit interrupt trigger level is set to 16 following a reset. It should be noted that the
user can set the transmit trigger levels by writing to the FCR register, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes
Table 3:
A2
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
[1]
0
0
0
Receive Holding Register
0
0
1
0
1
0
Interrupt Status Register
0
1
1
1
0
0
1
0
1
Line Status Register
1
1
0
Modem Status Register
1
1
1
Scratchpad Register
Baud rate register set (DLL/DLM)
[2]
0
0
0
LSB of Divisor Latch
0
0
1
MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)
[3]
0
1
0
Enhanced Feature Register
1
0
0
Xon1 word
1
0
1
Xon2 word
1
1
0
Xoff1 word
1
1
1
Xoff2 word
Internal registers decoding
A0
READ mode
A1
WRITE mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
n/a
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
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SC16C650AIA44 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 32-byte FIFO and infrared (IrDA) encoder/decoder
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SC16C650AIB48 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 32-byte FIFO and infrared (IrDA) encoder/decoder
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