參數(shù)資料
型號: SC16C652
廠商: NXP Semiconductors N.V.
英文描述: Dual UART with 32 bytes of transmit and receive FIFOs
中文描述: 雙UART,有32發(fā)送和接收FIFO字節(jié)
文件頁數(shù): 12/41頁
文件大小: 575K
代理商: SC16C652
Philips Semiconductors
SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Product data
Rev. 04 — 20 June 2003
12 of 41
9397 750 11634
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.9 DMA operation
The SC16C652 FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY
output pins. Tables
7
and
8
show this.
6.10 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally (see
Figure 4
). MCR[0-3] register bits are used for controlling loop-back
diagnostic testing. In the loop-back mode, the transmitter output (TX) and the receiver
input (RX) are disconnected from their associated interface pins, and instead are
connected together internally. The CTS, DSR, CD, and RI are disconnected from
Table 6:
Output
baud rate
Baud rate generator programming table using a 1.8432 MHz clock
Output
16
×
clock divisor
(decimal)
(HEX)
2304
900
1536
600
1047
417
768
300
384
180
192
C0
96
60
48
30
32
20
24
18
16
10
12
0C
6
06
3
03
2
02
1
01
Output
16
×
clock divisor
DLM
program value
(HEX)
09
06
04
03
01
00
00
00
00
00
00
00
00
00
00
00
DLL
program value
(HEX)
00
00
17
00
80
C0
60
30
20
18
10
0C
06
03
02
01
50
75
110
150
300
600
1200
2400
3600
4800
7200
9600
19.2 k
38.4 k
57.6 k
115.2 k
Table 7:
Non-DMA mode
1 = FIFO empty
0 = at least 1 byte in FIFO
Effect of DMA mode on state of RXRDY pin
DMA mode
0-to-1 transition when FIFO empties
1-to-0 transition when FIFO reaches trigger level,
or time-out occurs
Table 8:
Non-DMA mode
1 = at least 1 byte in FIFO
0 = FIFO empty
Effect of DMA mode on state of TXRDY pin
DMA mode
0-to-1 transition when FIFO becomes full
1-to-0 transition when FIFO goes below trigger level
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SC16C652IB48 Dual UART with 32 bytes of transmit and receive FIFOs
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