參數(shù)資料
型號: SC16C654BIBM
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.), with 64-byte FIFOs and infrared (IrDA) encoder-decoder
封裝: SC16C654BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html<1<Always Pb-free,;SC16C654BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html&
文件頁數(shù): 10/58頁
文件大?。?/td> 302K
代理商: SC16C654BIBM
9397 750 14965
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 20 June 2005
10 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
5.2 Pin description
Table 2:
Symbol
Pin description
Pin
PLCC68 LQFP64 HVQFN48 LFBGA6
Type Description
4
-
16/68
31
-
14
I
16/68 Interface type select (input with internal pull-up).
This input provides the 16 (Intel) or 68 (Motorola) bus
interface type select. The functions of IOR, IOW,
INTA to INTD, and CSA to CSD are re-assigned with the
logical state of this pin. When this pin is a logic 1, the
16 mode interface (16C654) is selected. When this pin is a
logic 0, the 68 mode interface (68C654) is selected. When
this pin is a logic 0, IOW is re-assigned to R/W, RESET is
re-assigned to RESET, IOR is not used, and INTA to INTD
are connected in a wire-OR configuration. The wire-OR
outputs are connected internally to the open-drain IRQ
signal output. This pin is not available on 64-pin packages
which operate in the 16 mode only.
Address 0 select bit.
Internal registers address selection in
16 and 68 modes.
Address 1 select bit.
Internal registers address selection in
16 and 68 modes.
Address 2 select bit.
Internal registers address selection in
16 and 68 modes.
Address 3, Address 4 select bits.
When the 68 mode is
selected, these pins are used to address or select individual
UARTs (providing CS is a logic 0). In the 16 mode, these
pins are re-assigned as chip selects, see CSB and CSC.
These pins are not available on 64-pin packages which
operate in the 16 mode only.
Carrier Detect (active LOW).
These inputs are associated
with individual UART channels A through D. A logic 0 on this
pin indicates that a carrier has been detected by the modem
for that channel.
A0
34
24
17
K5
I
A1
33
23
16
J5
I
A2
32
22
15
K4
I
A3
A4
20
50
-
-
9
31
-
-
I
CDA
CDB
CDC
CDD
CLKSEL
9
27
43
61
30
64
18
31
49
-
-
-
24
-
-
A1
K2
J9
A10
-
I
I
Clock Select.
The 1
×
or 4
×
pre-scalable clock is selected by
this pin. The 1
×
clock is selected when CLKSEL is a logic 1
(connected to V
CC
) or the 4
×
is selected when CLKSEL is a
logic 0 (connected to GND). MCR[7] can override the state
of this pin following reset or initialization (see MCR[7]). This
pin is not available on 64-pin packages which provide
MCR[7] selection only.
Chip Select (active LOW).
In the 68 mode, this pin
functions as a multiple channel chip enable. In this case, all
four UARTs (A to D) are enabled when the CS pin is a
logic 0. An individual UART channel is selected by the data
contents of address bits A[3:4]. when the 16 mode is
selected (68-pin devices), this pin functions as CSA (see
definition under CSA, CSB). This pin is not available on
64-pin packages which operate in the 16 mode only.
CS
16
-
5
-
I
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