參數(shù)資料
型號: SC16C750BIB64,128
廠商: NXP Semiconductors
文件頁數(shù): 44/44頁
文件大小: 0K
描述: IC UART 64BYTE 64LQFP
標準包裝: 1,500
通道數(shù): 1,UART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 935274403128
SC16C750BIB64-F
SC16C750BIB64-F-ND
SC16C750B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 October 2008
9 of 44
NXP Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
The rich feature set of the SC16C750B is available through internal registers. Automatic
hardware ow control, selectable transmit and receive FIFO trigger level, selectable TX
and RX baud rates, modem interface controls, and a sleep mode are some of these
features.
6.1 Internal registers
The SC16C750B provides 12 internal registers for monitoring and control. These registers
are shown in Table 3. These twelve registers are similar to those already available in the
standard 16C550. These registers function as data holding registers (THR/RHR), interrupt
status and control registers (IER/ISR), a FIFO Control Register (FCR), line status and
control registers (LCR/LSR), modem status and control registers (MCR/MSR),
programmable data rate (clock) control registers (DLL/DLM), and a user accessible
Scratchpad Register (SPR). Register functions are more fully described in the following
paragraphs.
[1]
These registers are accessible only when LCR[7] is a logic 0.
[2]
These registers are accessible only when LCR[7] is a logic 1.
Table 3.
Internal registers decoding
A2
A1
A0
READ mode
WRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]
0
Receive Holding Register
Transmit Holding Register
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
Line Control Register
1
0
Modem Control Register
1
0
1
Line Status Register
n/a
1
0
Modem Status Register
n/a
1
Scratchpad Register
Baud rate register set (DLL/DLM)[2]
0
LSB of Divisor Latch
0
1
MSB of Divisor Latch
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