參數(shù)資料
型號(hào): SC16C852LIBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
封裝: SC16C852LIB<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C852LIB<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1
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代理商: SC16C852LIBS
SC16C852L
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NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 February 2011
9 of 64
NXP Semiconductors
SC16C852L
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
INTA/IRQ
30
22
C5
O
When 16/68 pin is at logic 1 or unconnected, this output becomes
channel A interrupt output. The output state is defined by the user
through the software setting of MCR[3]. INTA is set to the active
mode and OP2A output to a logic 0 when MCR[3] is set to a
logic 1. INTA is set to the 3-state mode and OP2A is set to a logic 1
when MCR[3] is set to a logic 0.
When 16/68 pin is at logic 0, this output becomes device interrupt
output (active LOW, open-drain). An external pull-up resistor to
V
DD
is required.
When 16/68 pin is at logic 1 or unconnected, this output becomes
channel B interrupt output. The output state is defined by the user
through the software setting of MCR[3]. INTB is set to the active
mode and OP2B output to a logic 0 when MCR[3] is set to a
logic 1. INTB is set to the 3-state mode and OP2B is set to a
logic 1 when MCR[3] is set to a logic 0.
When 16/68 pin is at logic 0, this output is not used.
When 16/68 pin is at logic 1, this input becomes the read strobe
(active LOW). When 16/68 pin is at logic 0, this input pin is not
used and should be connected to V
DD
.
When 16/68 pin is at logic 1 or unconnected, this input becomes
the write strobe (active LOW).
When 16/68 pin is at logic 0, this input becomes read strobe when
it is at logic HIGH, and write strobe when it is at logic LOW.
Output 2 (user-defined).
This function is associated with
individual channels, A through B. The state at these pin(s) are
defined by the user and through MCR register bit 3. INTA, INTB
are set to the active mode and OP2x to logic 0 when MCR[3] is set
to a logic 1. INTA, INTB are set to the 3-state mode and OP2x to a
logic 1 when MCR[3] is set to a logic 0 (see
Table 21 “Modem
Control Register bits description”
, bit 3). Since these bits control
both the INTA, INTB operation and OP2x outputs, only one
function should be used at one time, INT or OP2.
Master Reset.
When 16/68 pin is at logic 1 or unconnected, this
input becomes the RESET pin (active HIGH).
When 16/68 pin is at logic LOW, this input pin becomes RESET
(active LOW). (See
Section 7.23 “SC16C852L external reset
condition and software reset”
for initialization details.)
Ring Indicator (active LOW).
These inputs are associated with
individual UART channels, A through B. A logic 0 on this pin
indicates the modem has received a ringing signal from the
telephone line. A logic 1 transition on this input pin will generate an
interrupt if modem status interrupt is enabled.
Request to Send (active LOW).
These outputs are associated
with individual UART channels, A through B. A logic 0 on the RTSx
pin indicates the transmitter has data ready and waiting to send.
Writing a logic 1 in the modem control register MCR[1] will set this
pin to a logic 0, indicating data is available. After a reset this pin
will be set to a logic 1.
INTB/n.c.
29
21
C6
O
IOR/V
DD
19
14
F4
I
IOW/R/W
15
12
F3
I
OP2A
OP2B
32
9
-
-
-
-
O
O
RESET/
RESET
36
24
A6
I
RIA
RIB
41
21
-
-
-
-
I
I
RTSA
RTSB
33
22
23
15
B6
F5
O
O
Table 2.
Symbol
Pin description
…continued
Pin
LQFP48
HVQFN32
Type
Description
TFBGA36
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