參數(shù)資料
型號(hào): SC16C852LIET
廠(chǎng)商: NXP Semiconductors N.V.
元件分類(lèi): 收發(fā)器
英文描述: 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
封裝: SC16C852LIB<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C852LIB<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1
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代理商: SC16C852LIET
SC16C852L
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NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 February 2011
29 of 64
NXP Semiconductors
SC16C852L
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
[1]
For 128-byte FIFO mode, refer to
Section 7.16
,
Section 7.17
,
Section 7.18
.
[2]
For 128-byte FIFO mode, refer to
Section 7.15
,
Section 7.17
,
Section 7.18
.
Table 13.
FCR[7]
0
0
1
1
[1]
When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see
Section 6.4 “FIFO operation”
).
Table 14.
FCR[5]
0
0
1
1
[1]
When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see
Section 6.4 “FIFO operation”
).
3
(cont.)
Transmit operation in mode ‘1’:
When the SC16C852L is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYA/TXRDYB pin will be a
logic 1 when the transmit FIFO is completely full; see
Section 6.10 “DMA
operation”
. It will be a logic 0 when the trigger level has been reached.
Receive operation in mode ‘1’:
When the SC16C852L is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,
or a Receive Time-Out has occurred, the RXRDYA/RXRDYB pin will go to a
logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
2
FCR[2]
1
FCR[1]
0
FCR[0]
RCVR trigger levels
FCR[6]
0
1
0
1
RX FIFO trigger level (bytes) in 32-byte FIFO mode
[1]
8
16
24
28
TX FIFO trigger levels
FCR[4]
0
1
0
1
TX FIFO trigger level (bytes) in 32-byte FIFO mode
[1]
16
8
24
30
Table 12.
Bit
FIFO Control Register bits description
…continued
Symbol
Description
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SC16C852LIET,118 功能描述:UART 接口集成電路 UART 2-CH 128Byte FIFO 1.8V 36-Pin RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C852LIET,151 功能描述:UART 接口集成電路 1.8V 2CH UART 128B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C852LIET,157 功能描述:UART 接口集成電路 1.8V 2CH UART 128B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C852LIET-G 功能描述:UART 接口集成電路 1.8V 2CH UART 128B FIFO 5MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel