參數(shù)資料
型號(hào): SC16IS740IPW,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 11/16頁(yè)
文件大?。?/td> 0K
描述: IC UART SINGLE W/FIFO 16-TSSOP
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 96
特點(diǎn): 低電流
通道數(shù): 1,UART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.5V, 3.3V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 828 (CN2011-ZH PDF)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名稱(chēng): 568-3648-5
935280988112
SC16IS740IPW
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN224C Rev. 1.0.9
4
SerD
es
FIN
224C
24-
B
it
Low-
P
ower
Serializer/D
eserializer
CKREF
STROBE
DP[8:1]
DP[16:9]
DP[17]
DP[18]
DP
DP[24:
S1
S2
DIRI
/DIRO
CKP
CKSO+
CKSO-
DSO+/DSI-
DSO-/DSI+
CKSI+
CKSI-
VDDP VDDS/A
/WE
DP[7:0]
DP[15:8]
A0
/CS0
/CS1
Reset
Baseband
Processor
GND
CKSI+
CKSI-
DSO-/DSI+
DSO+/DSI-
CKSO+
CKSO-
GND
Main Display
16-Bit Controller
/WE
DATA[7:0]
DATA[15:8]
A0
/CS0
VDDP VDDS/A
Serializer
FIN224C
Deserializer
FIN224C
1.8V
2.8V
CKP
DP[8:1]
DP[16:9]
DP
DP[18]
DP[19]
DP[24:20]
S1
S2
DIRI
/DIRO
CKREF
STROBE
2.8V
Main Display
8-Bit Controller
/WE
DATA[7:0]
A0
/CS1
Clock
Source
CKREF
STROBE
DP[
DP
DP[
DP[19]
DP[24:20]
S1
S2
DIRI
/DIRO
CKP
CKSO+
CKSO-
DSO+/DSI-
DSO-/DSI+
CKSI+
CKSI-
VDDP VDDS/A
/WE
DP[7:0]
DP[15:8]
A0
/CS0
/CS1
Reset
Baseband
Processor
GND
CKSI+
CKSI-
DSO-/DSI+
DSO+/DSI-
CKSO+
CKSO-
GND
Main Display
16-Bit Controller
/WE
DATA[7:0]
DATA[15:8]
A0
/CS0
VDDP VDDS/A
Serializer
FIN224C
Deserializer
FIN224C
1.8V
2.8V
CKP
DP
DP[:
DP[17]
DP
DP:
S1
S2
DIRI
/DIRO
CKREF
STROBE
2.8V
Main Display
8-Bit Controller
/WE
DATA[7:0]
A0
/CS1
Clock
Source
Figure 4. Dual-Display Controller Interface Block Diagram
Additional Application Information
Flex Cabling:
The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O
flex cable. The following best practices should be used when developing the flex cabling or Flex PCB.
Keep all four differential serial wires the same length.
Do not allow noisy signals over or near differential serial wires. Example: No CMOS traces over differential serial wires.
Design goal of 70 to 130
Ω differential characteristic impedance.
Do not place test points on differential serial wires.
Design differential serial wires a minimum of 2cm away from the antenna.
Visit Fairchild’s website at http://www.fairchildsemi.com/products/interface/userdes.html, contact your sales
representative, or contact Fairchild directly at interface@fairchildsemi.com for applications notes or flex guidelines.
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