參數(shù)資料
型號(hào): SC16IS752IBS
廠商: NXP Semiconductors N.V.
元件分類: 連接器件
英文描述: Dual UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝: SC16IS752IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;SC16IS752IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁(yè)數(shù): 30/60頁(yè)
文件大?。?/td> 356K
代理商: SC16IS752IBS
SC16IS752_SC16IS762
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NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 1 September 2011
30 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.13 Transmitter FIFO Level register (TXLVL)
This register is a read-only register. It reports the number of spaces available in the
transmit FIFO.
Table 24.
Bit
7
6:0
8.14 Receiver FIFO Level register (RXLVL)
This register is a read-only register, it reports the fill level of the receive FIFO, that is, the
number of characters in the RX FIFO.
Table 25.
Bit
7
6:0
8.15 Programmable I/O pins Direction register (IODir)
This register is used to program the I/O pins direction. Bit 0 to bit 7 controls GPIO0 to
GPIO7.
Table 26.
Bit
7:0
8.16 Programmable I/O pins State register (IOState)
When ‘read’, this register returns the actual state of all I/O pins. When ‘write’, each
register bit will be transferred to the corresponding I/O pin programmed as output.
Table 27.
Bit
7:0
Transmitter FIFO Level register bits description
Symbol
Description
-
not used; set to zeros
TXLVL[6:0]
number of spaces available in TX FIFO, from 0 (0x00) to 64 (0x40)
Receiver FIFO Level register bits description
Symbol
Description
-
not used; set to zeros
RXLVL[6:0]
number of characters stored in RX FIFO, from 0 (0x00) to 64 (0x40)
IODir register bits description
Symbol
IODir
Description
Set GPIO pins [7:0] to input or output.
0 = input
1 = output
IOState register bits description
Symbol
Description
IOState
Write this register: set the logic level on the output pins
0 = set output pin to zero
1 = set output pin to one
Read this register: return states of all pins
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