參數(shù)資料
型號: SC16IS762IBS
廠商: NXP Semiconductors N.V.
元件分類: 連接器件
英文描述: Dual UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝: SC16IS752IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;SC16IS752IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 17/60頁
文件大?。?/td> 356K
代理商: SC16IS762IBS
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 1 September 2011
17 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Figure 10
shows the internal prescaler and baud rate generator circuitry.
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the
least significant and most significant byte of the baud rate divisor. If DLL and DLH are both
zero, the UART is effectively disabled, as no baud clock will be generated.
Remark:
The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
Table 7
and
Table 8
show the baud rate and divisor correlation for crystal with frequency
1.8432 MHz and 3.072 MHz, respectively.
Figure 11
shows the crystal clock circuit reference.
Table 7.
Desired baud rate
(bit/s)
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
Fig 10. Prescaler and baud rate generator block diagram
Baud rates using a 1.8432 MHz crystal
Divisor used to generate
16
clock
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
Percent error difference
between desired and actual
0
0
0.026
0.058
0
0
0
0
0
0.69
0
0
0
0
0
0
0
2.86
BAUD RATE
GENERATOR
LOGIC
MCR[7] = 1
MCR[7] = 0
PRESCALER
LOGIC
(DIVIDE-BY-1)
INTERNAL
OSCILLATOR
LOGIC
002aaa233
XTAL1
XTAL2
input clock
PRESCALER
LOGIC
(DIVIDE-BY-4)
reference
clock
internal
baud rate
clock for
transmitter
and receiver
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