參數(shù)資料
型號: SC16IS762IPW,112
廠商: NXP Semiconductors
文件頁數(shù): 60/60頁
文件大小: 0K
描述: IC DUAL UART 64BYTE 28TSSOP
產(chǎn)品培訓(xùn)模塊: Bridge Solutions
Stand-Alone UARTs
I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標準包裝: 51
特點: 低電流
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.5V, 3.3V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名稱: 568-4021-5
935279294112
SC16IS762IPW
SC16IS762IPW-ND
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
9 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.2.1 Auto-RTS
Figure 5 shows RTS functional timing. The receiver FIFO trigger levels used in Auto-RTS
are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in
TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is de-asserted. The
sending device (for example, another UART) may send an additional character after the
trigger level is reached (assuming the sending UART has another character to send)
because it may not recognize the de-assertion of RTS until it has begun sending the
additional character. RTS is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This re-assertion allows the sending
device to resume transmission.
Fig 4.
Auto flow control (Auto-RTS and Auto-CTS) example
RX
FIFO
FLOW
CONTROL
TX
FIFO
PARALLEL
TO SERIAL
TX
FIFO
RX
FIFO
UART 1
UART 2
RX
TX
RTS
CTS
TX
RX
CTS
RTS
002aab656
SERIAL TO
PARALLEL
SERIAL TO
PARALLEL
FLOW
CONTROL
FLOW
CONTROL
FLOW
CONTROL
PARALLEL
TO SERIAL
(1) N = receiver FIFO trigger level.
(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in Section 7.2.1.
Fig 5.
RTS functional timing
start
character
N
start
character
N + 1
start
stop
RX
RTS
receive
FIFO
read
N
N + 1
12
002aab040
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