參數(shù)資料
型號： SC16IS762IPW-T
廠商： NXP Semiconductors
文件頁數(shù)： 5/60頁
文件大?。?/td> 0K
描述： IC UART DUAL I2C/SPI 28-TSSOP
標(biāo)準(zhǔn)包裝： 2,500
特點： 低電流
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.5V, 3.3V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
配用： 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
13 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.4 Hardware Reset, Power-On Reset (POR) and Software Reset
These three reset methods are identical and will reset the internal registers as indicated in
Table 4 summarizes the state of register after reset.
Remark: Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the
top-level reset signal RESET, POR and Software Reset, that is, they hold their
initialization values during reset.
Table 5 summarizes the state of output signals after reset.
Table 4.
Register reset
Register
Reset state
Interrupt Enable Register
all bits cleared
Interrupt Identification Register
bit 0 is set; all other bits cleared
FIFO Control Register
all bits cleared
Line Control Register
reset to 0001 1101 (0x1D)
Modem Control Register
all bits cleared
Line Status Register
bit 5 and bit 6 set; all other bits cleared
Modem Status Register
bits 3:0 cleared; bits 7:4 input signals
Enhanced Features Register
all bits cleared
Receive Holding Register
pointer logic cleared
Transmit Holding Register
pointer logic cleared
Transmission Control Register
all bits cleared
Trigger Level Register
all bits cleared
Transmit FIFO level
reset to 0100 0000 (0x40)
Receive FIFO level
all bits cleared
I/O direction
all bits cleared
I/O interrupt enable
all bits cleared
I/O control
all bits cleared
Extra Features Control Register
all bits cleared
Table 5.
Output signals after reset
Signal
Reset state
TX
HIGH
RTS
HIGH
I/Os
inputs
IRQ
HIGH by external pull-up
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