Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
22
I/O Port Control Channel B (IOPCRB)
IOPCR[xx]
IOPCRb[7:6]
IOPCRb[5:4]
IOPCRb[3:2]
IOPCRb[1:0]
Pin Control Bits
I/O3B
I/O2B
I/O1B
I/O0B
00 = input
IPR(7), TxC in
IPR(6), RxC in
IPR(3), TxC in
IPR(2), CTSN
01 = output
OPRab(7)
OPRab(6)
RTSN1 if IOPCR[5:4] = 01
OPRab(3)
RTSN2 if IOPCR[5:4]
≠ 01
OPRab(2)
10 = output
TxC 16x
RxC 1x
C/T ab out
TxC 1x
11 = output
TxC 1x
RxC 16x
RxC 1x
TxC 16x
I/O Port Control Channel C (IOPCRC)
IOPCR[xx]
IOPCRc[7:6]
IOPCRc[5:4]
IOPCRc[3:2]
IOPCRc[1:0]
Pin Control Bits
I/O3C
I/O2C
I/O1C
I/O0C
00 = input
IPR(5), TxC in
IPR(4), RxC in
IPR(1), C/Tcd Clk in1 TxC in
IPR(0), CTSN
01 = output
OPRcd(5)
OPRcd(4)
RTSN1 if IOPCR[5:4] = 01
OPRab(1)
RTSN2 if IOPCR[5:4]
≠ 01
OPRcd(0)
10 = output
TxC 16x
RxC 1x
RxC 16x
TxC 1x
11 = output
TxC 1x
RxC 16x
RxC 1x
TxC 16x
I/O Port Control Channel D (IOPCRD)
IOPCR[xx]
IOPCRd[7:6]
IOPCRd[5:4]
IOPCRd[3:2]
IOPCRd[1:0]
Pin Control Bits
I/O3D
I/O2D
I/O1D
I/O0D
00 = input
IPR(7), TxC in
IPR(6), RxC in
IPR(3), TxC in
IPR(2), CTSN
01 = output
OPRcd(7)
OPRcd(6)
RTSN1 if IOPCR[5:4] = 01
OPRcd(3)
RTSN2 if IOPCR[5:4]
≠ 01
OPRcd(2)
10 = output
TxC 16x
RxC 1x
C/T cd out
TxC 1x
11 = output
TxC 1x
RxC 16x
RxC 1x
TxC 16x
The input part of the I/O pins is always active. The programming of the IOPCR bits to 00 merely turns off the out drivers and places
the pin at high impedance.
A read of the IPR register returns the value of the IPR bits as shown above. IPR(5) is at bit position 5 of the data bus. Note that the IPR bit
positions do not follow the 0, 1, 2, 3 order of the I/O ports. During a read of the IPR the I/O ports are not latched. Therefore, it is possible to see
changing data during the read. Port pins that have clocks on them may not yield valid data during the read.
Since the input circuits of the I/O ports are always active it is possible to direct the port signal back into the port. For example: I/O1 will output
the RTS signal. Setting the Counter/Timer (C/T) to be clocked by the I/O1 port will result in the counter counting the number of times RTS goes
active. The change of state detectors on I/O0 and I/O1 will, when programmed, always be sensitive to the signal on the port regardless of the
source of that port’s signal.
NOTES:
1. Normal configurations place RTSN output on I/O1 and place Tx external clock input on I/O3. For the 48 pin Dual In-Line package, I/O3 is
not available. The following options allow flexible I/O programming with the 48 pin package:
When IOPCR(7:6), the I/O3 control,
≠ 00, then I/O1 becomes available to the transmitter as an external clock.
When IOPCR(5:4), the I/O2 control, = 01, then I/O2 may be the RTSN signal if MR1(7) = 1 and OPR(4) = 1.
2. I/O1 becomes RTSN when IOPCR(3:2) = 01 and MR1(7) = 1 and OPR(1) = 1. (OPR(3) for channel B)
3. Recommended method for setting RTS/CTS flow control is to set IPCR [5:4] to 01 and to set I/OPCR[1:0] to 00. This makes I/O[2} RTSN
and I/O[1] CTSN. Caution: When RTS/CTS is active writing to the OPR register could conflict with the receiver control of OPR [6] and
OPR [4].