參數(shù)資料
型號(hào): SC28L198A1A,512
廠商: NXP Semiconductors
文件頁數(shù): 38/57頁
文件大?。?/td> 0K
描述: IC UART OCTAL W/FIFO 84-PLCC
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 15
特點(diǎn): 故障啟動(dòng)位檢測
通道數(shù): 8
FIFO's: 16 字節(jié)
電源電壓: 3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 84-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 84-PLCC
包裝: 管件
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
其它名稱: 568-1117-5
935261323512
SC28L198A1A
Philips Semiconductors
Product data sheet
SC28L198
Octal UART for 3.3 V and 5 V supply voltage
2006 Aug 10
43
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (5V)
VCC = 5.0 volts " 10%; TA = –40 °C to +85°C; unless otherwise specified
SYMBOL
FIG #
PARAMETER
LIMIT
UNIT
MIN
TYP
MAX
Reset Timing
tRES1
RESET pulse width
10
Sclk
Bus Timing
tAS
A0–A7 setup time before Sclk C3 rising edge
10
2
ns
tAH
A0–A7 hold time after Sclk C3 rising edge
18
8
ns
tCS
CEN setup time before Sclk C1 high (Sync)
5
3
ns
CEN setup time before Sclk C2 high (Async)
5
3
ns
tCH
CEN hold time after Sclk C3 high (Sync)
14
1
Sclk
ns
CEN hold time after Sclk C4 high (Async)
25
1
Sclk
ns
tSTP
CEN high before next C2 to stop next cycle (Sync Mode)2
18
ns
tRWS
W–Rn setup time before Sclk C2 rising edge
5
ns
tRWH
W–Rn hold time after Sclk C3 rising edge
14
1
Sclk
ns
tDD
Read cycle Data valid after Sclk C3 rising edge
12
25
ns
tDF
Read cycle data bus floating after CEN high (Sync)
10
16
ns
Read cycle data bus floating after C4 end high (Async)
10
15
ns
tDS
Write cycle data setup time before Sclk C4 rising edge
25
14
ns
tDH
Write cycle data hold time after Sclk C4 rising edge
15
8
ns
tRWD
High time between CEN low (Async)
12
Sclk
ns
I/O Port Pin Timing
tPS
I/O input setup time before Sclk C3 rising edge
18
4
ns
tPH
I/O input hold time after Sclk C4 rising edge
12
1
ns
tPD
I/O output valid from:
Write Sclk C4 rising edge (write to IOPIOR)
32
50
ns
Interrupt Timing
tIR
IRQN from:
Internal interrupt source active bid
Reset to IRQN inactive
Write IMR (set or clear IMR bit)3
22
26
43
75
45
Sclk
ns
tDD
IACKN cycle Data valid after Sclk C3 rising edge
12
25
ns
Tx/Rx Clock Timing
tRX
RxC high or low time
15
8
ns
FRX4
RxC frequency (16 X)
(1 X)
0
16
1
Mhz
tTX
TxC high or low time
15
7
ns
FTX4
TxC frequency (16 X)
(1 X)
0
16
1
Mhz
Transmitter Timing
tTXD
TxD output delay from TxC low
32
60
ns
ttcs
TxC output delay from TxD output data
–15
4
15
ns
Receiver Timing
tRXS
RxD data setup time to RxC high (data)
20
–4
ns
tRXH
RxD data hold time from RxC high (data)
20
6
ns
tsSTRT
RxD data low time for receiving a valid Start Bit
17/32
bit
time
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