參數(shù)資料
型號: SC28L198A1BE,557
廠商: NXP Semiconductors
文件頁數(shù): 36/57頁
文件大小: 0K
描述: IC UART OCTAL W/FIFO 100-LQFP
產(chǎn)品培訓模塊: Stand-Alone UARTs
標準包裝: 450
特點: 故障啟動位檢測
通道數(shù): 8
FIFO's: 16 字節(jié)
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設(shè)備封裝: 100-LQFP(14x14)
包裝: 管件
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
其它名稱: 568-1210
935262731557
SC28L198A1BE
Philips Semiconductors
Product data sheet
SC28L198
Octal UART for 3.3 V and 5 V supply voltage
2006 Aug 10
41
RESET CONDITIONS
Device Configuration after Hardware Reset or CRa
cmd=x1F
Cleared registers:
Channel Status Registers (SR)
Channel Interrupt Status Registers (ISR)
Channel Interrupt Mask Registers (IMR)
Channel Interrupt Xon Status Register (XISR)
Interrupt Control Register (ICR)
Global Configuration Control Register (GCCR)
Hence the device enters the asynchronous bus cycling mode.
Current Interrupt Register (CIR)
BRG Timer Run Control Register (BRGTCR)
Watch-dog Timer Run Control Register (WDTRCR)
Channel Input/Output Port Configuration Registers (I/OPCR)
Hence all I/O pins have direction = Input after reset
BRG Counter/Timer Registers
Clears Modes for:
Power down
Test modes
Input Port Changed bits
Gang write to Xon or Xoff
Xon/Xoff/Address detection
Receiver error status
Disables:
Transmitters
Receivers
Interrupts, current and future
Halts:
BRG Counters
Bus cycle in progress (hardware RESET only)
Limitations:
Minimum RESETN pin pulse width is 10 SClk cycles after Vcc
reaches operational range
The user must allow a minimum of 6 SClk cycles to elapse after
a reset (RESETN pin or CRa initiated) of the device terminates
before initiating a new bus cycle.
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