參數(shù)資料
型號： SC28L91A1B,557
廠商： NXP Semiconductors
文件頁數(shù)： 7/30頁
文件大?。?/td> 0K
描述： IC UART SINGLE W/FIFO 44-PQFP
標準包裝： 480
系列： IMPACT
特點： 故障啟動位檢測
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
電源電壓： 3.3V，5V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調制解調器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應商設備封裝： 44-PQFP（10x10）
包裝： 托盤
其它名稱： 935267419557
SC28L91A1B
SC28L91A1B-ND
Philips Semiconductors
Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21
15
Unit
Max
Typ
Min
Parameter
Symbol
Receiver Timing, external clock (See Figure 13)
t*RXS
RxD data setup time to RxC high
50
10
ns
t*RXH
RxD data hold time from RxC high
50
10
ns
68000 or Motorola bus timing (See Figures 6, 7, 8)10
tDCR
DACKN Low (read cycle) from X1 High10
18
57
ns
tDCW
DACKN Low (write cycle) from X1 High
18
57
ns
tDAT
DACKN High impedance from CEN or IACKN High
10
15
ns
tCSC
CEN or IACKN setup time to X1 High for minimum DACKN cycle
30
10
ns
NOTES:
1. Parameters are valid over specified temperature and voltage range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: CL = 125 pF,
constant current source = 2.6 mA.
4. Typical values are the average values at +25
°C and 3.3 V.
5. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. Guaranteed by characterization of sample units.
7. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid.
8. Minimum frequencies are not tested but are guaranteed by design.
9. Clocks for 1X mode should maintain a 60/40 duty cycle or better.
10. Minimum DACKN time is tDCR = tDSC + tDCR + two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used
while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be
written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the
bus cycle. DACKN low or CEN high completes the write cycle.
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SC28L91A1B-S 功能描述:UART 接口集成電路 UART SINGLE W/FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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SC28L92 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter DUART
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