參數(shù)資料
型號(hào): SC28L92A1A,518
廠商: NXP Semiconductors
文件頁數(shù): 33/73頁
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 44-PLCC
標(biāo)準(zhǔn)包裝: 500
系列: IMPACT
特點(diǎn): 故障啟動(dòng)位檢測
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC
包裝: 帶卷 (TR)
其它名稱: 935263293518
SC28L92A1A-T
SC28L92A1A-T-ND
39
2552K–AVR–04/11
ATmega329/3290/649/6490
Write one to the JTD bit in MCUCSR.
The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is
not shifting data. If the hardware connected to the TDO pin does not pull up the logic level,
power consumption will increase. Note that the TDI pin for the next device in the scan chain con-
tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or
leaving the JTAG fuse unprogrammed disables the JTAG interface.
9.8
Register Description
9.8.1
SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in Table 9-2.
Note:
1. Standby mode is only recommended for use with external crystals or resonators.
Bit 1 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
Bit
765
4321
0
SM2
SM1
SM0
SE
SMCR
Read/Write
R
R/W
Initial Value
000
0000
0
Table 9-2.
Sleep Mode Select
SM2
SM1
SM0
Sleep Mode
000
Idle
001
ADC Noise Reduction
010
Power-down
011
Power-save
100
Reserved
101
Reserved
110
Standby(1)
111
Reserved
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