參數(shù)資料
型號: SC28L92A1BS,551
廠商: NXP Semiconductors
文件頁數(shù): 35/73頁
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 44PQFP
標準包裝: 490
系列: IMPACT
特點: 故障啟動位檢測
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-HVQFN EP(6x6)
包裝: 托盤
其它名稱: 935281063551
SC28L92A1BS-S
SC28L92A1BS-S-ND
40
2552K–AVR–04/11
ATmega329/3290/649/6490
9.8.2
PRR – Power Reduction Register
Bits 7, 6, 5 - Reserved bits
These bits are reserved bits in ATmega329/3290/649/6490 and will always read as zero.
Bit 4 - PRLCD: Power Reduction LCD
Writing logic one to this bit shuts down the LCD controller. The LCD controller must be disabled
and the display discharged before shut down. See "Disabling the LCD" on page 217 for details
on how to disable the LCD controller.
Bit 3 - PRTIM1: Power Reduction Timer/Counter1
Writing logic one to this bit shuts down the Timer/Counter1 module. When Timer/Counter1 is
enabled, operation will continue like before the shutdown.
Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface
Writing logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to
the module. When waking up the SPI again, the SPI should be re-initialized to ensure proper
operation.
Bit 1 - PRUSART: Power Reduction USART
Writing logic one to this bit shuts down the USART by stopping the clock to the module. When
waking up the USART again, the USART should be re-initialized to ensure proper operation.
Bit 0 - PRADC: Power Reduction ADC
Writing logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.
The analog comparator cannot use the ADC input MUX when the ADC is shut down.
Note:
The Analog Comparator is disabled using the ACD-bit in the “ACSR – Analog Comparator Control
Bit
7
6
5
4
3
210
PRLCD
PRTIM1
PRSPI
PRUSART0
PRADC
PRR
Read/Write
R
R/W
Initial Value
0
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