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參數(shù)資料
| 型號： | SC68C562C1A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS dual universal serial communications controller CDUSCC |
| 中文描述： | 2 CHANNEL(S), 10M bps, MULTI PROTOCOL CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, SOT238-3, LCC-52 |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 163K |
| 代理商： | SC68C562C1A |
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Philips Semiconductors
Product specification
SC68C562
CMOS Dual universal serial communications controller
(CDUSCC)
1998 Sep 04
7
PIN DESCRIPTION
(Continued)
MNEMONIC
PIN NO.
DIP
38, 11
TYPE
NAME AND FUNCTION
PLCC
42, 12
DCDA/BN,
SYNIA/BN
I
Channel A (B) Data Carrier Detected or External Sync Input:
The function of this pin is
programmable. As a DCD active-low input, it acts as an enable for the receiver or can be
used as a general purpose input. For the DCD function, the CDUSCC detects logic level
transitions on this pin and can be programmed to generate an interrupt when a transition
occurs. As an active-low external sync input, it is used in COP mode to obtain character
synchronization for the receiver without receipt of a SYN character. This mode can be
used in disc or tape controller applications or for the optional byte timing lead in X.21.
Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose
Output:
Active-low. For half-duplex DMA operation, this output indicates to the DMA
controller that one or more characters are available in the receiver FIFO (when the
receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled).
For full-duplex DMA operation, this output indicates to the DMA controller that data is
available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that
can be asserted and negated under program control.
Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send:
Active-low. For full-duplex DMA operation, this output indicates to the
DMA controller that the transmit FIFO is not full and can accept more data. When not in
full-duplex DMA mode, this pin can be programmed as a general purpose or a
Request-to-Send output, which can be asserted and negated under program control.
Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-low. For half-duplex single address operation, this input indicates to the CDUSCC
that the DMA controller has acquired the bus and that the requested bus cycle (read
receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter
is enabled) is beginning. For full-duplex single address DMA operation, this input indicates
to the CDUSCC that the DMA controller has acquired the bus and that the requested read
receiver FIFO bus cycle is beginning. Because the state of this input can be read under
program control, it can be used as a general purpose input when not in single address
DMA mode.
Channel A (B) Transmitter DMA Acknowledge or General Purpose Input:
Active-low.
When the channel is programmed for full-duplex single address DMA operation, this input
is asserted to indicate to the CDUSCC that the DMA controller has acquired the bus and
that the requested load transmitter FIFO bus cycle is beginning. Because the state of this
input can be read under program control, it can be used as a general purpose input when
not in full-duplex single address DMA mode.
Done:
Active-low, open-drain. DONEN can be used and is active in both DMA and
non-DMA modes. As an input, DONEN indicates the last DMA transfer cycle to the
TxFIFO. As an output, DONEN indicates either the last DMA transfer from the RxFIFO or
that the transmitted character count has reached terminal count.
Channel A (B) Sync Detect or Request-to-Send:
Active-low. If programmed as a sync
output, it is asserted one bit time after the specified sync character (COP or BISYNC
modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send
modem control signal, it functions as described previously for the TxDRQN/RTSN pin.
Data Transfer Acknowledge:
Active-low, 3-state. DTACKN is asserted on a write cycle to
indicate that the data on the bus has been latched, and on a read cycle or interrupt
acknowledge cycle to indicate valid data is on the bus. In a write bus cycle, input data is
latched by the assertion (falling edge) of DTACKN or by the negation (rising edge) of CSN,
whichever occurs first. The signal is negated when completion of the cycle is indicated by
negation of CSN or IACKN input, and returns to the inactive state (3-state) a short period
after it is negated. In single address DMA mode, input data is latched by the assertion
(falling edge) of DTCN or by the negation (rising edge) of the DMA acknowledge input,
whichever occurs first. DTACK is negated when completion of the cycle is indicated by the
assertion of DTCN or negation of DMA acknowledge inputs (whichever occurs first), and
returns to the inactive state (3-state) a short period after it is negated. When inactive,
DTACKN requires an external pull-up resistor.
Device Transfer Complete:
Active-low. DTCN is asserted by the DMA controller to
indicate that the requested data transfer is complete.
+5V Power Input
Signal and Power Ground Input
RTxDRQA/BN,
GPO1A/BN
34, 15
37, 17
O
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
33, 16
36, 18
O
RTxDAKA/BN,
GPI1A/BN
44, 5
48, 5
I
TxDAKA/BN,
GPI2A/BN
35, 14
38, 16
I
DONEN
27
29
I/O
RTSA/BN,
SYNOUTA/BN
41, 8
45, 9
O
DTACKN
22
24
O
DTC
23
25
I
V
CC
GND
48
24
34, 52
26, 13,
41, 7
I
I
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC68C562C1N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS dual universal serial communications controller CDUSCC |
| SC68C652B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, and 68 mode mP interface |
| SC68C652BIB48 | 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 32B FIFO MOT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC68C652BIB48,128 | 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 32B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC68C652BIB48,151 | 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 32B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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