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參數(shù)資料
| 型號(hào)： | SC87C451CCA68 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O |
| 中文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PEDESTAL, PLASTIC, MO-047AE, SOT-188-3, LCC-68 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大小： | 162K |
| 代理商： | SC87C451CCA68 |
Philips Semiconductors
Product specification
80C451/83C451/87C451
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
1998 May 01
7
CSR.3 Output Buffer Full Flag Clear Mode (OBFC) –
When
CSR.3 = 1, the positive edge of the ODS input clears the OBF flag.
When CSR.3 = 0, the negative edge of the ODS input clears the
OBF flag.
CSR.4, CSR.5 AFLAG Mode Select
(MA0, MA1) –
Bits 4 and 5 select the mode of operation for the
AFLAG pin as follows:
MA1 MA0
0 0
0 1
1 0
1 1
AFLAG Function
Logic 0 output
Logic 1 output
OBF flag output (CSR.1)
Select (SEL) input mode
The select (SEL) input mode is used to determine whether the port 6
data register or the control status register is output on port 6. When
the select feature is enabled, the AFLAG input controls the source of
port 6 output data. A logic 0 on AFLAG input selects the port 6 data
register, and a logic 1 on AFLAG input selects the control status
register.
CSR.6, CSR.7 BFLAG Mode Select
(MB0, MB1) –
Bits 6 and 7 select the mode operation as follows:
MB1 MB0
0 0
0 1
1 0
1 1
BFLAG Function
Logic 0 output
Logic 1 output
IBF flag output (CSR.0)
Port enable (PE)
In the port enable mode, IDS and ODS inputs are disabled when
BFLAG input is high. When the BFLAG input is low, the port is
enabled for I/O.
SPECIAL FUNCTION REGISTER ADDRESSES
The SFRs are identical to those of the standard 80C51 with the
exception of four registers that have been added to allow control of
the three additional I/O ports P4, P5, and P6. The additional
registers are P4, P5, P6, and CSR. Registers P4, P5, and P6
function as port latches for ports 4, 5, and 6, respectively. These
registers operate identically to those for ports 0 through 3 of the
80C51.
Table 1. Special Function Register Addresses
REGISTER ADDRESS
BIT ADDRESS
NAME
SYMBOL
ADDRESS
MSB
LSB
Port 4
Port 5
Port 6 data
Port 6 control status
P4
P5
P6
CSR
C0
C8
D8
E8
C7
CF
DF
EF
C6
CE
DE
EE
C5
CD
DD
ED
C4
CC
DC
EC
C3
CB
DB
EB
C2
CA
DA
EA
C1
C9
D9
E9
C0
C8
D8
E8
INTERNAL BUS
IDS
MODE
INPUT
BUFFER
(P6 READ)
OUTPUT
DRIVERS
BFLAG/ODS
MODE
(CSR.6/.7)
AFLAG
MODE
(CSR.4/.5)
MUX
CONTROL/STATUS
REGISTER (CSR)
OUTPUT BUFFER
(P6 WRITE)
INPUT BUFFER
FULL (CSR.0)
OUTPUT BUFFER
FULL (CSR.1)
EDGE/LEVEL
SELECT (CSR.2)
IDS
ODS
BFLAG
AFLAG
PORT 6
SU00087
Figure 1. Port 6 Block Diagram
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