參數(shù)資料
型號: SCAN12100
廠商: National Semiconductor Corporation
英文描述: 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement
中文描述: 1228.8和614.4 Mbps的CPRI串行解串器與自動重新同步和高精度延遲校準測量
文件頁數(shù): 5/14頁
文件大小: 217K
代理商: SCAN12100
Pin #
96
97
Pin Name
SPMODE [0]
SPMODE [1]
I/O, Type
I, LVTTL or 1.8V
LVCMOS Internal
pull down
Description
Speed mode configuration. (OPMODE must be low)
Pulling both pins low enables MDIO control.
SPMODE [1]
SPMODE [0]
0
0
0
1
1
0
1
1
Enable 10-bit mode
The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2
0 = Selects 8-bit mode. Enables the internal 8b/10b encoder and decoder.
1 = Selects 10-bit mode. Bypasses internal 8b/10b encoder and decoder.
Loop back configuration.
Pulling both pins low enables MDIO control.
Note: During Special line (remote) loop back mode, the output de-emphasis control
is disabled.
LOOP [1]
LOOP [0]
0
0
Normal mode—no loop back
0
1
Line (remote) loop back mode
1
0
Local loop back mode
1
1
Special line (remote) loop back mode
Rate selected via MDIO
614.4 Mbps rate mode
1228.8 Mbps rate mode
Reserved
98
TENBMODE
I, LVTTL or 1.8V
LVCMOS, Internal
pull down
99
100
LOOP [0]
LOOP [1]
I, LVTTL or 1.8V
LVCMOS, Internal
pull down
MDC/MDIO
30
31
37
36
35
34
33
IEEE 1149.1 (JTAG)
45
41
44
43
46
RESERVED PINS
83
84
POWER
9, 15, 20,
32, 38, 47,
85
8, 14, 21,
42
1, 2, 28, 29 PVDD33
50, 51, 76,
87
GROUND
3, 4, 5, 10,
13, 16, 19,
24, 25, 26,
27, 39, 40,
48, 49, 63,
75, 86
MDC
MDIO
ADD0
ADD1
ADD2
ADD3
ADD4
3.3V LVTTL
Internal pull up on
ADDR pins
MDC/MDIO configuration bus.
Protocol per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL
compatible, not 1.2V signal compatible.
TDI
TDO
TMS
TCK
TRSTB
3.3V LVTTL
Internal pull up on
TDI, TMS, and
TRSTB
JTAG test bus for IEEE 1149.1 and 1149.6 support.
RES1
RES2
I
Reserved.
Tie with 5 K
resistor to ground.
AVDD18
I, Power
1.8V analog supply.
AVDD33
I, Power
3.3V analog supply.
I, Power
I, Power
3.3V PLL supply (minimize supply noise to < 100 mV peak-to-peak).
1.8V or 3.3V parallel I/O bus and control pin supply.
See VSEL pin description for additional information.
IOVDD
GND
I, Ground
Device ground.
5
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