參數(shù)資料
型號: SCAN15MB200TSQX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6
中文描述: DUAL LINE TRANSCEIVER, PQCC48
封裝: LLP-48
文件頁數(shù): 2/12頁
文件大?。?/td> 599K
代理商: SCAN15MB200TSQX
Pin Descriptions
Pin
Name
SWITCH SIDE DIFFERENTIAL INPUTS
SIA_0+
SIA_0
29
SIA_1+
SIA_1
20
SIB_0+
SIB_0
27
SIB_1+
SIB_1
22
LINE SIDE DIFFERENTIAL INPUTS
LI_0+
LI_0
39
LI_1+
LI_1
10
SWITCH SIDE DIFFERENTIAL OUTPUTS
SOA_0+
SOA_0
33
SOA_1+
SOA_1
16
SOB_0+
SOB_0
31
SOB_1+
SOB_1
18
LINE SIDE DIFFERENTIAL OUTPUTS
LO_0+
LO_0
41
LO_1+
LO_1
8
DIGITAL CONTROL INTERFACE
MUX_S0
MUX_S1
11
PREA_0
PREA_1
PREB_0
PREB_1
24
PREL_0
PREL_1
5
ENA_0
ENA_1
ENB_0
ENB_1
14
ENL_0
ENL_1
4
TDI
2
TDO
1
TMS
46
TCK
47
TRST
3
POWER
LLP Pin
Number
I/O, Type
Description
30
I, LVDS
Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS,
CML, or LVPECL compatible.
Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS,
CML, or LVPECL compatible.
Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS,
CML, or LVPECL compatible.
Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS,
CML, or LVPECL compatible.
19
I, LVDS
28
I, LVDS
21
I, LVDS
40
I, LVDS
Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
9
I, LVDS
34
O, LVDS
Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible
(Notes 1, 3).
Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible
(Notes 1, 3).
Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible
(Notes 1, 3).
Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible
(Notes 1, 3).
15
O, LVDS
32
O, LVDS
17
O, LVDS
42
O, LVDS
Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes
1, 3).
Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes
1, 3).
7
O, LVDS
38
I, LVTTL
Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed
through to the Line-side.
Output pre-emphasis control for Switch-side outputs. Each output driver on the Switch A-side
and B-side has a separate pin to control the pre-emphasis on or off.
26
23
25
I, LVTTL
44
I, LVTTL
Output pre-emphasis control for Line-side outputs. Each output driver on the Line A-side and
B-side has a separate pin to control the pre-emphasis on or off.
Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side
and B-side has a separate enable pin.
36
13
35
I, LVTTL
45
I, LVTTL
Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a
separate enable pin.
Test Data Input to support IEEE 1149.1 features
O, LVTTL Test Data Output to support IEEE 1149.1 features
I, LVTTL
Test Mode Select to support IEEE 1149.1 features
I, LVTTL
Test Clock to support IEEE 1149.1 features
I, LVTTL
Test Reset to support IEEE 1149.1 features
I, LVTTL
S
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