
Register Descriptions
(Continued)
TABLE 7. Mode Register Control of LSPN
(Continued)
Scan Chain Configuration (if unparked)
TDI
B
→
Register
→
LSP
0
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
1
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
0
→
PAD
→
LSP
1
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
2
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
0
→
PAD
→
LSP
2
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
1
→
PAD
→
LSP
2
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
0
→
PAD
→
LSP
1
→
PAD
→
LSP
2
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
3
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
0
→
PAD
→
LSP
3
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
1
→
PAD
→
LSP
3
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
0
→
PAD
→
LSP
1
→
PAD
→
LSP
5
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
2
→
PAD
→
LSP
3
→
PAD
→
TDO
B
...
TDI
B
→
Register
→
LSP
0
→
PAD
→
LSP
1
→
PAD
→
LSP
2
→
PAD
→
LSP
3
→
PAD
→
LSP
4
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
5
→
PAD
→
TDO
B
Mode Register(s)
MR0: X000X001
MR0: X000X010
MR0: X000X011
MR0: X000X100
MR0: X000X101
MR0: X000X110
MR0: X000X111
MR0: X010X000
MR0: X010X001
MR0: X010X010
MR0: X010X011
MR0: X010X100
...
MR0: X110X111
MR0: X000X000
MR1: XXXXX001
(Note 10)
MR0: X000X001
MR1: XXXXX001
(Note 10)
MR0: X000X010
MR1: XXXXX001
(Note 10)
...
MR0: X110X111
MR1: XXXXX001
(Note 10)
MR0: X000X000
MR1: XXXXX010
(Note 10)
...
MR0: X110X111
MR1: XXXXX111
(Note 10)
MR0: XXX1XXXX
MR1: XXXXXXXX
(Note 10)
TDI
B
→
Register
→
LSP
0
→
PAD
→
LSP
5
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
1
→
PAD
→
LSP
5
→
PAD
→
TDO
B
...
TDI
B
→
Register
→
LSP
0
→
PAD
→→
LSP
1
→
PAD
→
LSP
2
→
PAD
→
LSP
3
→
PAD
→
LSP
4
→
PAD
→
LSP
5
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
6
→
PAD
→
TDO
B
...
TDI
B
→
Register
→
LSP
0
→
PAD
→
LSP
1
→
PAD
→
LSP
2
→
PAD
→
LSP
3
→
PAD
→
LSP
4
→
PAD
→
LSP
5
→
PAD
→
LSP
6
→
PAD
→
LSP
7
→
PAD
→
TDO
B
TDI
B
→
Register
→
TDO
B
(Loopback)
Note 10:
Mode Register
1
is only available in the HDL version (up to eight LSPs). The Silicon version has three LSPs and uses Mode Register
0
only.
Note 11:
In a device with 8 LSPs there are 2
8
possible LSPN configurations: No LSPs, each individual LSP, combinations of 2 to 7 LSPs, and all 8 LSPs.
TABLE 8. Test Clock Configuration
Bit 3
1
0
1
0
X
LSP n
Parked
Parked
Unparked
Unparked
Parked-TLR
TCK n
Stopped
Free-running
Free-running
Free-running
Stopped after 512 clock pulses
Bit 3 is normally set to logic 0 so that TCK
is free-running
when the local scan ports are parked in the
Parked-RTI
,
Parked-Pause-DR
or
Parked-Pause-IR
state. When the local
ports are parked, bit 3 can be programmed with logic 1,
forcing all of the LSP TCK
’s to stop. This feature can be
used in power sensitive applications to reduce the power
consumed by the test circuitry in parts of the system that are
not under test. When in the
Parked-TLR
state, TCK
is gated
(stopped) after 512 clock pulses have been received on
TCK
B
independent of the bit 3 value.
Bit 7 is a status bit for the TCK counter. Bit 7 is only set (logic
1) when the TCK counter is on and has reached terminal
S
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