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參數(shù)資料
| 型號(hào)： | SCC2681AE1A44,518 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 26/29頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DUART SOT187-2 |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 特點(diǎn)： | 故障啟動(dòng)位檢測(cè) |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 3 位 |
| 電源電壓： | 5V |
| 帶并行端口： | 是 |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 935274518518 SCC2681AE1A44-T SCC2681AE1A44-T-ND |
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Philips Semiconductors
Product data
SCC2681
Dual asynchronous receiver/transmitter (DUART)
2004 Apr 06
6
AC CHARACTERISTICS
Tamb = –40 °C to +85 °C1; VCC = +5.0 V ± 10% 2, 3, 4, 5
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
Min
Typ
Max
UNIT
Reset Timing (Figure 3)
tRES
RESET pulse width
200
–
ns
Bus Timing (Figure 4)6
tAS
A0-A3 set-up time to RDN, WRN LOW
10
–
ns
tAH
A0-A3 hold time from RDN, WRN LOW
100
–
ns
tCS
CEN set-up time to RDN, WRN LOW
0
–
ns
tCH
CEN hold time from RDN, WRN HIGH
0
–
ns
tRW
WRN, RDN pulse width
225
–
ns
tDD
Data valid after RDN LOW
–
175
ns
tDF
Data bus floating after RDN HIGH
–
100
ns
tDS
Data set-up time before WRN HIGH
100
–
ns
tDH
Data hold time after WRN HIGH
20
–
ns
tRWD
HIGH time between READs and/or WRITE7, 8
200
–
ns
Port Timing (Figure 5)6
tPS
Port input set-up time before RDN LOW
0
–
ns
tPH
Port input hold time after RDN HIGH
0
–
ns
tPD
Port output valid after WRN HIGH
–
400
ns
Interrupt Timing (Figure 6)
tIR
INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
–
300
ns
Write THR (TxRDY interrupt)
–
300
ns
Reset command (delta break interrupt)
–
300
ns
Stop C/T command (counter interrupt)
–
300
ns
Read IPCR (input port change interrupt)
–
300
ns
Write IMR (clear of interrupt mask bit)
–
300
ns
Clock Timing (Figure 7)10
tCLK
X1/CLK HIGH or LOW time
100
–
ns
fCLK
X1/CLK frequency
1.0
3.6864
4.0
MHz
tCTC
CTCLK (IP2) HIGH or LOW time
100
–
ns
fCTC
CTCLK (IP2) frequency
0
–
4.0
MHz
tRX9
RxC HIGH or LOW time
220
–
ns
fRX9
RxC frequency (16
×)
(1
×)
0
–
2.0
1.0
MHz
tTX9
TxC HIGH or LOW time
220
–
ns
fTX9
TxC frequency (16
×)
(1
×)
0
–
2.0
1.0
MHz
Transmitter Timing (Figure 8)
tTXD9
TxD output delay from TxC external clock input on IP pin
–
350
ns
tTCS9
Output delay from TxC LOW at OP pin to TxD data output
0
–
150
ns
Receiver Timing (Figure 10)
tRXS9
RxD data setup time before RxC HIGH at external clock input on IP pin
240
–
ns
tRXH9
RxD data hold time after RxC HIGH at external clock input on IP pin
200
–
ns
NOTES:
1. For operating at elevated temperatures, the device must be derated based on +150
°C maximum junction temperature.
2. Parameters are valid over specified temperature range.
3. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with a
transition time of
≤ 20 ns. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of
0.8 V and 2.0 V as appropriate.
4. Typical values are at +25
°C, typical supply voltages, and typical processing parameters.
5. Test condition for outputs: CL = 150 pF, except interrupt outputs. Test condition for interrupt outputs: CL = 50 pF, RL = 2.7 k to VCC.
6. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
case, all timing specifications apply referenced to the falling and rising edges of CEN, CEN and RDN (also CEN and WRN) are ANDed
internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle.
7. If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid.
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