參數(shù)資料
型號: SCC2681T
廠商: NXP Semiconductors N.V.
英文描述: Dual asynchronous receiver/transmitter (DUART)
中文描述: 雙異步接收器/發(fā)送器(杜阿爾特)
文件頁數(shù): 9/15頁
文件大?。?/td> 108K
代理商: SCC2681T
Philips Semiconductors
Product data
SCC2681T
Dual asynchronous receiver/transmitter (DUART)
2004 Apr 06
9
4. Test conditions for outputs: C
L
= 150 pF, except interrupt outputs. Test conditions for interrupt outputs: C
L
= 50 pF, R
L
= 2.7 k
to V
CC
.
5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must
be negated for t
EHEL
to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the
RDN input even if the CEN is used as the strobing signal for bus operations.
7. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
8. Minimum frequencies are not tested but are guaranteed by design.
SD00028
RESET
t
RES
Figure 3. Reset Timing
A0–A3
CEN
(READ)
t
AVEL
RDN
D0–D7
(READ)
FLOAT
FLOAT
VALID
INVALID
CEN
(WRITE)
VALID
D0–D7
(WRITE)
t
ELAX
t
EHEL
t
RLRH
t
RHDF
t
RHDI
t
RLDV
t
RLDA
t
EHEL
t
WLWH
WRN
t
DVWH
t
WHDI
SD00100
Figure 4. Bus Timing
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