參數(shù)資料
型號(hào): SCC2698B
廠商: NXP Semiconductors N.V.
英文描述: Enhanced octal universal asynchronous receiver/transmitter (Octal UART)(增強(qiáng)型八通用異步接收器/傳送器)
中文描述: 增強(qiáng)八進(jìn)制通用異步接收器/發(fā)送器(八路的UART)(增強(qiáng)型八通用異步接收器/傳送器)
文件頁數(shù): 19/29頁
文件大?。?/td> 167K
代理商: SCC2698B
Philips Semiconductors
Product specification
SCC2698B
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
2000 Jan 31
19
DC ELECTRICAL CHARACTERISTICS
1, 2, 3
T
A
= 0 to +70 , V
CC
= 5.0 V
10%, –40 to 85 C
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Typ
UNIT
Min
Max
0.8
V
IL
V
IH
V
IH
Input low voltage
Input high voltage (except X1/CLK)
Input high voltage (X1/CLK)
V
V
V
2.0
0.8V
CC
V
OL
V
OH
Output Low voltage
Output High voltage (except OD outputs)
I
OL
= 2.4mA
I
OH
= –400
μ
A
I
OH
= –100
μ
A
V
IN
= 0
V
IN
= V
CC
V
IN
= 0 to V
CC
V
IN
= GND, X2 = open
V
IN
= V
CC
, X2 = open
V
IN
= V
CC
V
IN
= 0
V
IN
= V
CC
V
IN
= 0
0.8V
CC
0.9V
CC
–50
0.4
V
V
V
μ
A
μ
A
μ
A
μ
A
μ
A
I
IL
I
IH
I
I
I
ILX1
I
IHX1
I
OZH
I
OZL
I
ODL
I
ODH
Input current Low, MPI and MPP pins
Input current High, MPI and MPP pins
Input leakage current
20
–10
10
X1/CLK input Low current
X1/CLK input High current
Output off current High, 3-State data bus
Output off current Low, 3-State data bus
Open-drain output Low current in off state: IRQN
Open-drain output Low current in off state: IRQN
Power supply current
Operating mode
Power down mode
9
–100
100
10
–10
μ
A
–10
10
μ
A
I
CC
30
mA
2.0
mA
NOTES:
1. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 20ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of V
IL
and V
IH
, as
appropriate.
3. Typical values are at +25
°
C, typical supply voltages, and typical processing parameters.
4. Test condition for interrupt and MPP outputs: C
= 50pF, R
= 2.7k
to V
. Test conditions for rest of outputs: C
= 150pF.
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum high times between one CEN and the next. The RDN signal must
be negated for t
RWD
guarantee that any status register changes are valid.
7. Consecutive write operations to the command register require at least three edges of the X1 clock between writes.
8. This value is not tested, but is guaranteed by design.
9. See UART applications note for power down currents less than 5
μ
A.
10.Operation to 0MHz is assured by design. Minimum test frequency is 2MHz.
11. Address is latched on leading edge of read or write cycle.
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