參數(shù)資料
型號： SCC2698BC1A84,512
廠商： NXP Semiconductors
文件頁數(shù)： 5/29頁
文件大小： 0K
描述： IC UART OCTAL ENHANCED 84-PLCC
產(chǎn)品培訓模塊： Stand-Alone UARTs
標準包裝： 15
特點： 故障啟動位檢測
通道數(shù)： 8
FIFO's： 3 位
電源電壓： 5V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 84-LCC（J 形引線）
供應商設備封裝： 84-PLCC
包裝： 管件
產(chǎn)品目錄頁面： 828 (CN2011-ZH PDF)
其它名稱： 568-1120-5
933976250512
SCC2698BC1A84
Philips Semiconductors
Product data sheet
SCC2698B
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
2006 Aug 07
13
Table 2. Register Bit Formats
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MR1 (Mode Register 1)
RxRTS
Control
RxINT Select
Error Mode*
Parity Mode
Parity Type
Bits per Character
0 = No
0 = RxRDY
0 = Char
00 = With parity
0 = Even
00 = 5
1 = Yes
1 = FFULL
1 = Block
01 = Force parity
1 = Odd
01 = 6
10 = No parity
10 = 7
11 = Special mode
11 = 8
NOTE: *In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
MR2 (Mode Register 2)
Channel Mode
TxRTS
Control
CTS Enable
Tx
Stop Bit Length*
00 = Normal
0 = 0.563
4 = 0.813
8 = 1.563
C = 1.813
01 = Auto-echo
0 = No
1 = 0.625
5 = 0.875
9 = 1.625
C = 1.875
10 = Local loop
1 = Yes
2 = 0.688
6 = 0.938
A = 1.688
E = 1.938
11 = Remote loop
3 = 0.750
7 = 1.000
B = 1.750
F = 2.000
NOTE: *Add 0.5 to values shown above for 0–7, if channel is programmed for 5 bits/char.
CR (Command Register)
Miscellaneous Commands
Disable Tx
Enable Tx
Disable Rx
Enable Rx
See text
0 = No
See text
1 = Yes
NOTE: Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. A disabled transmitter
cannot be loaded
SR (Status Register)
Rec’d Break*
Framing
Error*
Parity Error*
Overrun Error
TxEMT
TxRDY
FFULL
RxRDY
0 = No
1 = Yes
NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status register provides these
bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a reset error status command. In character mode, they
must be reset when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by
using the error reset command (command 4x) or a receiver reset.
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