參數(shù)資料
型號(hào): SCC2698BC1A84,518
廠商: NXP Semiconductors
文件頁(yè)數(shù): 19/29頁(yè)
文件大小: 0K
描述: IC UART OCTAL ENHANCED SOT189
標(biāo)準(zhǔn)包裝: 250
特點(diǎn): 故障啟動(dòng)位檢測(cè)
通道數(shù): 8
FIFO's: 3 位
電源電壓: 5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 84-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 84-PLCC
包裝: 帶卷 (TR)
其它名稱: 933976250518
SCC2698BC1A84-T
SCC2698BC1A84-T-ND
Philips Semiconductors
Product data sheet
SCC2698B
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
2006 Aug 07
26
Table 5.
Baud Rates Extended
Normal BRG
BRG Test
CSR[7:4]
ACR[7] = 0
ACR[7] = 1
ACR[7] = 0
ACR[7] = 1
0000
50
75
4,800
7,200
0001
110
880
0010
134.5
38.4K
1,076
38.4K
0011
200
150
19.2K
14.4K
0100
300
28.8K
0101
600
57.6K
0110
1,200
115.2K
0111
1,050
2,000
1,050
2,000
1000
2,400
57.6K
1001
4,800
1010
7,200
1,800
57.6K
14.4K
1011
9,600
1100
38.4K
19.2K
38.4K
19.2K
1101
Timer
1110
I/O2 – 16X
1111
I/O2 – 1X
NOTE:
Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left. This
change affects all receivers and transmitters on the DUART.
The test mode at address H‘A’ changes all transmitters and receivers to the 1x mode and connects the output ports to some internal nodes.
Receiver Reset in the Normal Mode (Receiver Enabled)
Reset can be accomplished easily by issuing a receiver software or hardware reset followed by a receiver enable. All receiver data,
status and programming will be preserved and available before reset. The reset will NOT affect the programming.
Receiver Reset in the Wake-Up Mode (MR1[4:3] = 11)
Reset can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software or
hardware reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and
available before reset. The reset will NOT affect other programming.
The reason for this is the receiver is partially enabled when the parity bits are at ‘11’. Thus the receiver disable and reset is bypassed by
the partial enabling of the receiver.
SD00097
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