參數(shù)資料
型號： SCC68692C1A44,512
廠商： NXP Semiconductors
文件頁數(shù)： 24/28頁
文件大?。?/td> 0K
描述： IC UART DUAL 44-PLCC
產品培訓模塊： Stand-Alone UARTs
標準包裝： 26
特點： 故障啟動位檢測
通道數(shù)： 2，DUART
FIFO's： 3 位
電源電壓： 5V
帶并行端口： 是
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應商設備封裝： 44-PLCC
包裝： 管件
產品目錄頁面： 828 (CN2011-ZH PDF)
其它名稱： 568-1121-5
933977630512
SCC68692C1A44
Philips Semiconductors
Product data
SCC68692
Dual asynchronous receiver/transmitter (DUART)
2004 Mar 03
5
PIN DESCRIPTION
SYMBOL
PIN NO.
TYPE
NAME AND FUNCTION
D0–D7
25,16,24,17
23,18,22,19
I/O
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the DUART
and the CPU. D0 is the least significant bit.
CSN
35
I
Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU and the DUART are
enabled on D0–D7 as controlled by the R/WN and A1–A4 inputs. When CEN is HIGH, the DUART places
the D0–D7 lines in the 3-State condition.
R/WN
8
I
Read/Write: A HIGH input indicates a read cycle and a LOW input indicates a write cycle, when a cycle is
initiated by assertion of the CSN input.
A1–A4
1,2,5,6
I
Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESETN
34
I
Reset: A LOW level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex
0F, puts OP0–OP7 in the HIGH state, stops the counter/timer, and puts Channels A and B in the inactive
state, with the TxDA and TxDB outputs in the mark (HIGH) state. Resets Test Mode, sets MR pointer to MR1.
DTACKN
9
O
Data Transfer Acknowledge: 3-State active-LOW output asserted in write, read, or interrupt cycles to
indicate proper transfer of data between the CPU and the DUART.
INTRN
21
O
Interrupt Request: Active-LOW, open-drain output which signals the CPU that one or more of the eight
maskable interrupting conditions are true.
IACKN
37
I
Interrupt Acknowledge: Active-LOW input indicating an interrupt acknowledge cycle. In response, the
DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.
X1/CLK
32
I
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 9, Clock Timing.
X2
33
I
Crystal 2: Crystal connection. See Figure 9. If a crystal is not used it is best to keep this pin not connected
although it is permissible to ground it.
RxDA
31
I
Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is HIGH, “space” is LOW.
RxDB
10
I
Channel B Receive Serial Data Input: The least significant bit is received first. “Mark” is HIGH, “space” is LOW.
TxDA
30
O
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held
in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback mode.
“Mark” is HIGH, “space” is LOW.
TxDB
11
O
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held
in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode.
‘Mark’ is HIGH, ‘space’ is LOW.
OP0
29
O
Output 0: General purpose output or Channel A request to send (RTSAN, active-LOW). Can be
deactivated automatically on receive or transmit.
OP1
12
O
Output 1: General purpose output or Channel B request to send (RTSBN, active-LOW). Can be
deactivated automatically on receive or transmit.
OP2
28
O
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver
1X clock output.
OP3
13
O
Output 3: General purpose output or open-drain, active-LOW counter/timer output or Channel B transmitter
1X clock output, or Channel B receiver 1X clock output.
OP4
27
O
Output 4: General purpose output or Channel A open-drain, active-LOW, RxRDYAN/FFULLAN output.
OP5
14
O
Output 5: General purpose output or Channel B open-drain, active-LOW, RxRDYBN/FFULLBN output.
OP6
26
O
Output 6: General purpose output or Channel A open-drain, active-LOW, TxRDYAN output.
OP7
15
O
Output 7: General purpose output or Channel B open-drain, active-LOW, TxRDYBN output.
IP0
7
I
Input 0: General purpose input or Channel A clear to send active-LOW input (CTSAN). Pin has an internal
VCC pull-up device supplying 1 to 4 A of current.
IP1
4
I
Input 1: General purpose input or Channel B clear to send active-LOW input (CTSBN). Pin has an internal
VCC pull-up device supplying 1 to 4 A of current.
IP2
36
I
Input 2: General purpose input or Channel B receiver external clock input (RxCB), or counter/timer external
clock input. When external clock is used by the receiver, the received data is sampled on the rising edge of
the clock. Pin has an internal VCC pull-up device supplying 1 to 4 A of current.
IP3
2
I
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 A of current.
IP4
39
I
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock
is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal
VCC pull-up device supplying 1 to 4 A of current.
IP5
38
I
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 A of current.
VCC
40
I
Power Supply: +5 V supply input.
GND
20
I
Ground
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相關代理商/技術參數(shù)
參數(shù)描述
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SCC68692C1A44-T 制造商:NXP Semiconductors 功能描述:UART 2-CH 5V 44-Pin PLCC
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