參數(shù)資料
型號(hào)： SCC68692C1A44,518
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 0K
描述： IC DUART 44PLCC
標(biāo)準(zhǔn)包裝： 500
特點(diǎn)： 故障啟動(dòng)位檢測(cè)
通道數(shù)： 2，DUART
FIFO's： 3 位
電源電壓： 5V
帶并行端口： 是
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC
包裝： 帶卷 (TR)
其它名稱： 933977630518
SCC68692C1A44-T
SCC68692C1A44-T-ND
Philips Semiconductors
Product data
SCC68692
Dual asynchronous receiver/transmitter (DUART)
2004 Mar 03
15
CSRA – Channel A Clock Select Register
CSRA[7:4] – Channel A Receiver Clock Select
This field selects the baud rate clock for the Channel A transmitter.
The field definition is shown in Table 3.
CSRA[3:0] – Channel A Transmitter Clock Select
This field selects the baud rate clock for the Channel A transmitter.
The field definition is as shown in Table 3, except as follows:
CSRA[3:0]
ACR[7] = 0
Baud Rate ACR[7] = 1
1110
1111
IP3–16X
IP3–1X
IP3–16X
IP3–1X
The transmitter clock is always a 16X clock except for
CSRA[3:0] = 1111.
CSRB – Channel B Clock Select Register
CSRB[7:4] – Channel B Receiver Clock Select
This field selects the baud rate clock for the Channel B receiver. The
field definition is as shown in Table 3, except as follows:
CSRB[7:4]
ACR[7] = 0
Baud Rate ACR[7] = 1
1110
1111
IP2–16X
IP2–1X
IP2–16X
IP2–1X
The receiver clock is always a 16X clock except for
CSRB[7:4] = 1111.
CSRB[3:0] – Channel B Transmitter Clock Select
This field selects the baud rate clock for the Channel B transmitter.
The field definition is as shown in Table 3, except as follows:
CSRB[3:0]
ACR[7] = 0
Baud Rate ACR[7] = 1
1110
1111
IP5–16X
IP5–1X
IP5–16X
IP5–1X
The transmitter clock is always a 16X clock except for
CSRB[3:0] = 1111.
CRA – Channel A Command Register
CRA is a register used to supply commands to Channel A. Multiple
commands can be specified in a single write to CRA as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
NOTE: Access to the upper four bits of the command register
should be separated by three (3) edges of the X1 clock.
CRA[7:4] – Miscellaneous Commands
The encoded value of this field may be used to specify a single
command as follows:
0000
No command.
0001
Reset MR pointer. Causes the Channel A MR pointer to point to MR1.
0010
Reset receiver. Resets the Channel A receiver as if a hardware reset had been ap-
plied. The receiver is disabled and the FIFO is flushed.
0011
Reset transmitter. Resets the Channel A transmitter as if a hardware reset had been
applied.
0100
Reset error status. Clears the Channel A Received Break, Parity Error, and Overrun
Error bits in the status register (SRA[7:4]). Used in character mode to clear OE status
(although RB, PE and FE bits will also be cleared) and in block mode to clear all error
status after a block of data has been received.
0101
Reset Channel A break change interrupt. Causes the Channel A break detect
change bit in the interrupt status register (ISR[2]) to be cleared to zero.
0110
Start break. Forces the TxDA output LOW (spacing). If the transmitter is empty the
start of the break condition will be delayed up to two bit times. If the transmitter is ac-
tive the break begins when transmission of the character is completed. If a character
is in the THR, the start of the break will be delayed until that character, or any other
loaded subsequently are transmitted. The transmitter must be enabled for this com-
mand to be accepted.
0111
Stop break. The TxDA line will go HIGH (marking) within two bit times. TxDA will re-
main HIGH for one bit time before the next character, if any, is transmitted.
1000
Assert RTSN. Causes the RTSN output to be asserted (LOW).
1001
Negate RTSN. Causes the RTSN output to be negated (HIGH).
1010
Set Timeout Mode On. The receiver in this channel will restart the C/T as each re-
ceive character is transferred from the shift register to the RHR. The C/T is placed
in the counter mode, the START/STOP counter commands are disabled, the counter
is stopped, and the Counter Ready Bit, ISR[3], is reset.
1011
Not used.
1100
Disable Timeout Mode. This command returns control of the C/T to the regular
START/STOP counter commands. It does not stop the counter, or clear any pending
interrupts. After disabling the timeout mode, a ‘Stop Counter’ command should be
issued
1101
Not used.
1110
Power Down Mode On. In this mode, the DUART oscillator is stopped and all func-
tions requiring this clock are suspended. The execution of commands other than dis-
able power down mode (1111) requires a X1/CLK. While in the power down mode,
do not issue any commands to the CR except the disable power down mode com-
mand. It is recommended that the transmitter and receiver be disabled prior to plac-
ing the DUART into power down mode. This command is in CRA only. Design Note:
The part will not output DTACKN while in power down mode. Use automatic DTACKN
generation.
1111
Disable Power Down Mode. This command restarts the oscillator. After invoking this
command, wait for the oscillator to start up before writing further commands to the
CR. This command is in CRA only.
CRA[3] – Disable Channel A Transmitter
This command terminates transmitter operation and reset the
TxDRY and TxEMT status bits. However, if a character is being
transmitted or if a character is in the THR when the transmitter is
disabled, the transmission of the character(s) is completed before
assuming the inactive state.
CRA[2] – Enable Channel A Transmitter
Enables operation of the Channel A transmitter. The TxRDY status
bit will be asserted.
CRA[1] – Disable Channel A Receiver
This command terminates operation of the receiver immediately – a
character being received will be lost. The command has no effect on
the receiver status bits or any other control registers. If the special
multidrop mode is programmed, the receiver operates even if it is
disabled. See Operation section.
CRA[0] – Enable Channel A Receiver
Enables operation of the Channel A receiver. If not in the special
wake up mode, this also forces the receiver into the search for start
bit state.
CRB – Channel B Command Register
CRB is a register used to supply commands to Channel B. Multiple
commands can be specified in a single write to CRB as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
The bit definitions for this register are identical to the bit definitions
for CRA, with the exception of commands “Ex” and “Fx” which are
used for power down mode. These two commands are not used in
CRB. All other control actions that apply to CRA also apply to CRB.
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