參數(shù)資料
型號(hào)： SCC68692C1A44,529
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 5/28頁(yè)
文件大小： 0K
描述： IC DUART 44PLCC
標(biāo)準(zhǔn)包裝： 26
特點(diǎn)： 故障啟動(dòng)位檢測(cè)
通道數(shù)： 2，DUART
FIFO's： 3 位
電源電壓： 5V
帶并行端口： 是
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC
包裝： 管件
其它名稱(chēng)： 933977630529
SCC68692C1A44-S
SCC68692C1A44-S-ND
Philips Semiconductors
Product data
SCC68692
Dual asynchronous receiver/transmitter (DUART)
2004 Mar 03
13
Table 2.
Register Bit Formats
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MR1A
RxRTS
CONTROL
RxINT
SELECT
ERROR
MODE*
PARITY MODE
PARITY
TYPE
BITS PER
CHARACTER
MR1A
MR1B
0 = No
1 = Yes
0 = RxRDY
1 = FFULL
0 = Char
1 = Block
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
0 = Even
1 = Odd
00 = 5
01 = 6
10 = 7
11 = 8
NOTE:
*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MR2A
CHANNEL MODE
TxRTS
CONTROL
CTS
ENABLE Tx
STOP BIT LENGTH*
MR2A
MR2B
00 = Normal
01 = Auto-Echo
10 = Local loop
11 = Remote loop
0 = No
1 = Yes
0 = No
1 = Yes
0 = 0.563
4 = 0.813
8 = 1.563
C = 1.813
1 = 0.625
5 = 0.875
9 = 1.625
D = 1.875
2 = 0.688
6 = 0.938
A = 1.688
E = 1.938
3 = 0.750
7 = 1.000
B = 1.750
F = 2.000
NOTE: *Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.
CSRA
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CSRA
CSRB
RECEIVER CLOCK SELECT
TRANSMITTER CLOCK SELECT
CSRB
See Text
* See Table 6 for BRG Test frequencies in this data sheet, and
“Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CRA
CRB
MISCELLANEOUS COMMANDS
DISABLE Tx
ENABLE Tx
DISABLE Rx
ENABLE Rx
CRB
See Text
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
NOTE: Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SRA
SRB
RECEIVED
BREAK*
FRAMING
ERROR*
PARITY
ERROR*
OVERRUN
ERROR
TxEMT
TxRDY
FFULL
RxRDY
SRB
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits
(7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are
discarded when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using
the error reset command (command 4x) or a receiver reset.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OP7
OP6
OP5
OP4
OP3
OP2
OPCR
0 = OPR[7]
1 = TxRDYB
0 = OPR[6]
1 = TxRDYA
0 = OPR[5]
1 = RxRDY/
FFULLB
0 = OPR[4]
1 = RxRDY/
FFULLA
00 = OPR[3]
01 = C/T OUTPUT
10 = TxCB(1x)
11 = RxCB(1x)
00 = OPR[2]
01 = TxCA(16x)
10 = TxCA(1x)
11 = RxCA(1x)
OPR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OPR bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OP pin
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
NOTE:
The level at the OP pin is the inverse of the bit in the OPR register.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BRG SET
SELECT
COUNTER/TIMER
MODE AND SOURCE
DELTA
IP3 INT
DELTA
IP2 INT
DELTA
IP1 INT
DELTA
IP0 INT
ACR
0 = set 1
1 = set 2
See Table 4
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
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