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參數(shù)資料

型號(hào)：	SCC68692C1F40
廠商：	NXP SEMICONDUCTORS
元件分類(lèi)：	微控制器/微處理器
英文描述：	Dual asynchronous receiver/transmitter DUART
中文描述：	2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CDIP40
文件頁(yè)數(shù)：	5/30頁(yè)
文件大?。?/td>	193K
代理商：	SCC68692C1F40

Philips Semiconductors

Product specification

SCC68692

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

PIN DESCRIPTION

SYMBOL

D0–D7

PIN NO.

25,16,24,17

23,18,22,19

TYPE

I/O

NAME AND FUNCTION

Data Bus:

Bidirectional 3-State data bus used to transfer commands, data and status between the

DUART and the CPU. D0 is the least significant bit.

Chip Enable:

Active-Low input signal. When Low, data transfers between the CPU and the DUART are

enabled on D0–D7 as controlled by the R/WN and A1–A4 inputs. When CEN is High, the DUART places

the D0–D7 lines in the 3-State condition.

Read/Write:

A High input indicates a read cycle and a low input indicates a write cycle, when a cycle is

initiated by assertion of the CSN input.

Address Inputs:

Select the DUART internal registers and ports for read/write operations.

Reset:

A Low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex

0F, puts OP0–OP7 in the High state, stops the counter/timer, and puts Channels A and B in the inactive

state, with the TxDA and TxDB outputs in the mark (High) state. Resets Test Mode, sets MR pointer to MR1.

Data Transfer Acknowledge:

3-State active-Low output asserted in write, read, or interrupt cycles to

indicate proper transfer of data between the CPU and the DUART.

Interrupt Request:

Active-Low, open-drain output which signals the CPU that one or more of the eight

maskable interrupting conditions are true.

Interrupt Acknowledge:

Active-Low input indicating an interrupt acknowledge cycle. In response, the

DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.

Crystal 1:

Crystal connection or an external clock input. A crystal of a clock the appropriate frequency

(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 9, Clock Timing.

Crystal 2:

Crystal connection. See Figure 9. If a crystal is not used it is best to keep this pin not connected

although it is permissible to ground it.

Channel A Receiver Serial Data Input:

The least significant bit is received first. “Mark” is High, “space” is Low.

Channel B Receive Serial Data Input:

The least significant bit is received first. “Mark” is High, “space” is Low.

Channel A Transmitter Serial Data Output:

The least significant bit is transmitted first. This output is

held in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback

mode. “Mark” is High, “space” is Low.

Channel B Transmitter Serial Data Output:

The least significant bit is transmitted first. This output is

held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback

mode. ‘Mark’ is High, ‘space’ is Low.

Output 0:

General purpose output or Channel A request to send (RTSAN, active-Low). Can be

deactivated automatically on receive or transmit.

Output 1:

General purpose output or Channel B request to send (RTSBN, active-Low). Can be

deactivated automatically on receive or transmit.

Output 2:

General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A

receiver 1X clock output.

Output 3:

General purpose output or open-drain, active-Low counter/timer output or Channel B

transmitter 1X clock output, or Channel B receiver 1X clock output.

Output 4:

General purpose output or Channel A open-drain, active-Low, RxRDYAN/FFULLAN output.

Output 5:

General purpose output or Channel B open-drain, active-Low, RxRDYBN/FFULLBN output.

Output 6:

General purpose output or Channel A open-drain, active-Low, TxRDYAN output.

Output 7:

General purpose output or Channel B open-drain, active-Low, TxRDYBN output.

Input 0:

General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an internal