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參數(shù)資料
| 型號： | SCE5782 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 顯示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, HIGH EFFICIENCY RED, 4.57 mm |
| 封裝： | PLASTIC, DIP-26 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SCE5782 |
2001 OSRAM Opto Semiconductors Inc. San Jose, CA
SCE5780/1/2/3/4/5/6
www.inneon.com/opto 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG Regensburg, Germany
www.osram-os.com +49-941-202-7178
8
August 1, 2001-18
character location and the succeeding seven bytes are row data.
The row data represents the status (On, Off) of individual col-
umn LEDs. Figure 8c shows that each 8 bit word is formatted to
represent Character Address, or Column Data.
Figure 8d shows the sequence for loading the bytes of data.
Bringing the LOAD line low enables the serial register to accept
data. The shift action occurs on the low to high transition of the
serial data clock (SDCLK). The least signicant bit (D0) is loaded
rst. After eight clock pulses the LOAD line is brought high.
With this transition the OPCODE is decoded. The decoded
OPCODE directs D4–D0 to be latched in the Character Address
register, stored in the RAM as Column data, or latched in the
Control Word register. The control IC requires a minimum 600
ns delay between successive byte loads. As indicated in Figure
8a, a total of 512 bits of data are required to load all eight char-
acters into the display.
The Character Address Register selects the character address
that the row and column data will be written to. See Table 2 for
opcode and character addressing. After loading the Character
Address Register, the next seven bytes load the column data,
one row at a time, starting with row 0 (top row) and ending with
row 6 (bottom row). Each character address has a 7 x 5 bit User
RAM formatted as seven rows, each containing ve column
data bits. The three most signicant bits, D7–D5 represent the
opcode for the row data and the least signicant ve bits, D4–
D0 represent the column data. See Table 3 for the column data
format. If an address is loaded before all seven rows are written,
the next column data will be loaded into Row 0 of the new
address. The remaining rows of the old address are not changed.
Table 1 shows the Row Address for the example character,
“D.” Column data is written and read asynchronously from the
280 bit RAM. Once loaded, the internal oscillator and character
multiplexer reads the data from the RAM. These characters are
row strobed with column data as shown in Figures 9 and 10.
The character strobe rate is determined by the internal or user
supplied external MUX Clock and the ICs÷ 320 counter.
Table 1. Character “D”
Figure 8. Loading Serial Character Data
Op code
D7 D6 D5
Column Data
D4 D3 D2 D1 D0
C0 C1 C2 C3 C4
Hex
Row 0
0
1
0
1E
Row 1
0
1
0
1
11
Row 2
0
1
0
1
11
Row 3
0
1
0
1
11
Row 4
0
1
0
1
11
Row 5
0
1
0
1
11
Row 6
0
1
0
1E
Character 0
Character 1
Character 2
Character 3
Character 4
Character 5
Character 6
Character 7
Example: Serial Clock=5.0 MHz, Clock Period=200 ns
Time between LOADS
LOAD
Serial
Clock
DATA
Clock
Period
t0
D0
D1
D2
D3
D4
D5
D6
D7
11 Clock Cycles, 2.2
s
Time
Between
Loads
600 ns(min)
Character Address
OPCODE
Column Data
D0
D
D1
D
D2
D
D3
D
D4
D
11 Clock Cycles, 2.2
s
Character 0
Address
Row 0 Column
Data
88 Clock Cycles, 17.6
s
704 Clock Cycles, 140.8
s
Row 1 Column
Data
Row 2 Column
Data
Row 3 Column
Data
Row 4 Column
Data
D0
0
D1
0
D2
0
D3
0
D4
0
D5
1
D6
0
D7
1
a.
b.
c.
d.
Row 5 Column
Data
Row 6 Column
Data
D5
0
D6
0
D7
0
Time
Between
Loads
600 ns(min)
OPCODE
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