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參數(shù)資料
| 型號(hào)： | SCM6341ZP15A |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 24 Bit Static Random Access Memory |
| 中文描述： | 128K X 24 STANDARD SRAM, 15 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大?。?/td> | 124K |
| 代理商： | SCM6341ZP15A |
MCM6341
8
MOTOROLA FAST SRAM
WRITE CYCLE 2
(E Controlled; See Notes 1, 2, 3, and 4)
Parameter
Symbol
b l
MCM6341–10
MCM6341–11
MCM6341–12
MCM6341–15
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tAVAV
tAVEL
tAVEH
tAVEH
10
—
11
—
12
—
15
—
ns
5
Address Setup Time
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write
9
—
10
—
10
—
12
—
ns
Address Valid to End of Write (G
High)
8
—
9
—
9
—
10
—
ns
Enable Pulse Width
tELEH,
tELWH
9
—
10
—
10
—
12
—
ns
6, 7
Enable Pulse Width (G High)
tELEH,
tELWH
8
—
9
—
9
—
10
—
ns
6, 7
Data Valid to End of Write
tDVEH
tEHDX
tEHAX
4
—
5
—
5
—
6
—
ns
Data Hold Time
0
—
0
—
0
—
0
—
ns
Write Recovery Time
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
5. All write cycle timing is referenced from the last valid address to the first transitioning address.
6. If E goes low coincident with or after W goes low, the output will remain in a high–impedance condition.
7. If E goes high coincident with or before W goes high, the output will remain in a high–impedance condition.
DATA VALID
HIGH–Z
tAVAV
tAVEH
tAVEL
tELWH
tEHAX
tDVEH
tEHDX
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
tELEH
WRITE CYCLE 2
(E Controlled; See Notes 1, 2, 3, and 4)
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