參數(shù)資料
型號(hào)： SCN2681AC1N40
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： Dual asynchronous receiver/transmitter DUART
中文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 6/30頁(yè)
文件大?。?/td> 205K
代理商： SCN2681AC1N40
Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
6
AC CHARACTERISTICS
T
A
= -40
°
C to +85
°
C
1
, V
CC
= +5.0V
10%
2, 3, 4, 5
SYMBOL
PARAMETER
LIMITS
Typ
UNIT
Min
Max
Reset Timing (Figure 3)
t
RES
Bus Timing (Figure 4)
6
t
AS
t
AH
t
CS
t
CH
t
RW
t
DD
t
DF
t
DS
t
DH
t
RWD
Port Timing (Figure 5)
6
t
PS
t
PH
t
PD
Interrupt Timing (Figure 6)
t
IR
RESET pulse width
200
ns
A0-A3 setup time to RDN, WRN Low
A0-A3 hold time from RDN, WRN Low
CEN setup time to RDN, WRN Low
CEN hold time from RDN, WRN High
WRN, RDN pulse width
Data valid after RDN Low
Data bus floating after RDN High
Data setup time before WRN High
Data hold time after WRN High
High time between READs and/or WRITE
7, 8
10
100
0
0
225
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
175
100
100
20
200
Port input setup time before RDN Low
Port input hold time after RDN High
Port output valid after WRN High
0
0
ns
ns
ns
400
INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (delta break interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
Clock Timing (Figure 7)
10
t
CLK
X1/CLK High or Low time
f
CLK
X1/CLK frequency
t
CTC
CTCLK (IP2) High or Low time
f
CTC
CTCLK (IP2) frequency
t
RX9
RxC High or Low time
f
RX9
RxC frequency (16X)
(1X)
t
TX9
TxC High or Low time
f
TX9
TxC frequency (16X)
(1X)
Transmitter Timing (Figure 8)
t
TXD9
TxD output delay from TxC external clock input on IP pin
t
TCS9
Output delay from TxC low at OP pin to TxD data output
Receiver Timing (Figure 10)
t
RXS9
RxD data setup time before RxC high at external clock input on IP pin
t
RXH9
RxD data hold time after RxC high at external clock input on IP pin
NOTES:
1. For operating at elevated temperatures, the device must be derated based on +150
°
C maximum junction temperature.
2. Parameters are valid over specified temperature range.
3. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
transition time of < 20ns. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V
and 2.0V as appropriate.
4. Typical values are at +25
°
C, typical supply voltages, and typical processing parameters.
5. Test condition for outputs: C
L
= 150pF, except interrupt outputs. Test condition for interrupt outputs: C
L
= 50pF, R
L
= 2.7k
to V
CC
.
6. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
case, all timing specifications apply referenced to the falling and rising edges of CEN, CEN and RDN (also CEN and WRN) are ANDed
internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle.
7. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for t
RWD
to guarantee that any status register changes are valid.
8. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
9. This parameter is not applicable to the 28-pin device.
10.Operation to 0MHz is assured by design. However, operation at low frequencies is not tested and has not been characterized.
300
300
300
300
300
300
ns
ns
ns
ns
ns
ns
100
2.0
100
0
220
0
0
220
0
0
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
3.6864
4.0
4.0
2.0
1.0
2.0
1.0
350
150
ns
ns
0
240
200
ns
ns
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