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參數(shù)資料
| 型號： | SCN2681AE1N40 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Dual asynchronous receiver/transmitter DUART |
| 中文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 12/30頁 |
| 文件大小： | 205K |
| 代理商： | SCN2681AE1N40 |
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Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
12
Table 2. Register Bit Formats
(Continued)
BIT 7
BRG SET
SELECT
0 = set 1
1 = set 2
BIT 6 BIT 5 BIT 4
COUNTER/TIMER
MODE AND SOURCE
BIT 3
DELTA
IP 3 INT
0 = Off
1 = On
BIT 2
DELTA
IP 2 INT
0 = Off
1 = On
BIT 1
DELTA
IP 1 INT
0 = Off
1 = On
BIT 0
DELTA
IP 0 INT
0 = Off
1 = On
ACR
See Table 4
BIT 7
DELTA
IP 3
0 = No
1 = Yes
BIT 6
DELTA
IP 2
0 = No
1 = Yes
BIT 5
DELTA
IP 1
0 = No
1 = Yes
BIT 4
DELTA
IP 0
0 = No
1 = Yes
BIT 3
BIT 2
BIT 1
BIT 0
IPCR
IP 3
IP 2
IP 1
IP 0
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
BIT 7
INPUT
PORT
CHANGE
0 = No
1 = Yes
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ISR
DELTA
BREAK B
RxRDY/
FFULLB
TxRDYB
COUNTER
READY
DELTA
BREAK A
RxRDY/
FFULLA
TxRDYA
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
BIT 7
IN. PORT
CHANGE
INT
0 = Off
1 = On
BIT 6
DELTA
BREAK B
INT
0 = Off
1 = On
BIT 5
RxRDY/
FFULLB
INT
0 = Off
1 = On
BIT 4
BIT 3
BIT 2
DELTA
BREAK A
INT
0 = Off
1 = On
BIT 1
RxRDY/
FFULLA
INT
0 = Off
1 = On
BIT 0
IMR
TxRDYB
INT
COUNTER
READY
INT
0 = Off
1 = On
TxRDYA
INT
0 = Off
1 = On
0 = Off
1 = On
BIT 7
C/T[15]
BIT 6
C/T[14]
BIT 5
C/T[13]
BIT 4
C/T[12]
BIT 3
C/T[11]
BIT 2
C/T[10]
BIT 1
C/T[9]
BIT 0
C/T[8]
CTUR
BIT 7
C/T[7]
BIT 6
C/T[6]
BIT 5
C/T[5]
BIT 4
C/T[4]
BIT 3
C/T[3]
BIT 2
C/T[2]
BIT 1
C/T[1]
BIT 0
C/T[0]
CTLR
MR1A – Channel A Mode Register 1
MR1A is accessed when the Channel A MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRA. After reading or writing MR1A, the pointer will
point to MR2A.
MR1A[7] – Channel A Receiver Request-to-Send Control
This bit controls the deactivation of the RTSAN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR1A[7] = 1 causes RTSAN to be
negated upon receipt of a valid start bit if the Channel A FIFO is full.
However, OPR[0] is not reset and RTSAN will be asserted again
when an empty FIFO position is available. This feature can be used
for flow control to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input of the transmitting
device.
MR1A[6] – Channel A Receiver Interrupt Select
This bit selects either the Channel A receiver ready status (RxRDY)
or the Channel A FIFO full status (FFULL) to be used for CPU
interrupts. It also causes the selected bit to be output on OP4 if it is
programmed as an interrupt output via the OPCR.
MR1A[5] – Channel A Error Mode Select
This bit select the operating mode of the three FIFOed status bits
(FE, PE, received break) for Channel A. In the ‘character’ mode,
status is provided on a character-by-character basis; the status
applies only to the character at the top of the FIFO. In the ‘block”
mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command for Channel
A was issued.
MR1A[4:3| – Channel A Parity Mode Select
If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] + 11 selects Channel A to operate in the
special multidrop mode described in the Operation section.
MR1A[2] – Channel A Parity Type Select
This bit selects the parity type (odd or even) if the ‘with parity’ mode
is programmed by MR1A[4:3], and the polarity of the forced parity bit
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special multidrop mode it
selects the polarity of the A/D bit.
MR1A[1:0] – Channel A Bits Per Character Select
This field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
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