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參數(shù)資料
| 型號(hào)： | SCN2681TC1A44 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Dual asynchronous receiver/transmitter DUART |
| 中文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 7/14頁(yè) |
| 文件大?。?/td> | 114K |
| 代理商： | SCN2681TC1A44 |
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Philips Semiconductors
Product specification
SCN2681T
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
7
SYMBOL
PARAMETER
LIMITS
UNIT
Min
1.0
Max
t
RES
Reset pulse width
μ
s
A0–A3
CEN
(READ)
t
AVEL
RDN
D0–D7
(READ)
FLOAT
FLOAT
VALID
INVALID
CEN
(WRITE)
VALID
D0–D7
(WRITE)
t
ELAX
t
EHEL
t
RLRH
t
RHDF
t
RHDI
t
RLDV
t
RLDA
t
EHEL
t
WLWH
WRN
t
DVWH
t
WHDI
SD00100
Figure 4. Bus Timing
SYMBOL
PARAMETER
1
LIMITS
UNIT
Min
0
100
120
110
15
Max
t
AVEL
t
ELAX
t
RLRH
t
EHEL
t
RLDA
t
RLDV
t
RHDI
t
RHDF
t
WLWH
t
DVWH
t
WHDI
A0–A3 setup to RDN and CEN, or WRN and CEN low
RDN and CEN, or WRN and CEN low to A0–A3 invalid
RDN and CEN low to RDN or CEN high
CEN high to CEN low
2, 3
CEN and RDN low to data outputs active
CEN and RDN low to data valid
CEN or RDN high to data invalid
CEN or RDN high to data outputs floating
WRN and CEN low to WRN or CEN high
Data input valid to WRN or CEN high
WRN or CEN high to data invalid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
10
65
75
35
15
NOTES:
1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
2. If CEN is used as the ‘strobing’ input, the parameter defines the minimum high times between one CEN and the next. The RDN signal must
be negated for t
EHEL
to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the
RDN input even if the CEN is used as the strobing signal for bus operations.
3. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
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