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參數(shù)資料
| 型號： | SCN2681TC1N40 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Dual asynchronous receiver/transmitter DUART |
| 中文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 114K |
| 代理商： | SCN2681TC1N40 |
Philips Semiconductors
Product specification
SCN2681T
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
8
RDN
IP0–IP6
WRN
OP0–OP7
t
PS
t
PH
OLD DATA
NEW DATA
(a) INPUT PINS
t
PD
(b) OUTPUT PINS
SD00101
Figure 5. Port Timing
SYMBOL
1
PARAMETER
LIMITS
UNIT
Min
0
0
Max
t
PS
t
PH
t
PD
Port input setup time before RDN low
Port input hold time after RDN high
Port output valid after WRN high
ns
ns
ns
200
NOTE:
1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
NOTES:
1.
2.
INTRN or OP3-OP7 when used as interrupt outputs.
The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
signal, V
, to a point 0.5V above V
. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and
test environment are pronounced and can greatly affect the resultant measurement.
V
M
V
OL
+0.5V
V
OL
WRN
INTERRUPT
1
OUTPUT
t
IR
SD00102
Figure 6. Interrupt Timing
SYMBOL
PARAMETER
LIMITS
UNIT
Min
Max
INTRN (or OP3–OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (delta break interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
200
200
200
200
200
200
ns
ns
ns
ns
ns
ns
t
IR
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