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參數(shù)資料
| 型號： | SCN68681 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual universal asynchronous receiver/transmitter (DUART）(雙通用異步接收器/傳送器) |
| 中文描述： | 雙路通用異步接收器/發(fā)送器（杜阿爾特）（雙通用異步接收器/傳送器） |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 187K |
| 代理商： | SCN68681 |
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Philips Semiconductors
Product specification
SCN68681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
14
If an external 1X clock is used for the transmitter, MR2A[3] = 0
selects one stop bit and MR2A[3] = 1 selects two stop bits to be
transmitted.
MR1B – Channel B Mode Register 1
MR1B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRB. After reading or writing MR1B, the pointer will
point to MR2B.
The bit definitions for this register are identical to MR1A, except that
all control actions apply to the Channel B receiver and transmitter
and the corresponding inputs and outputs.
MR2B – Channel B Mode Register 2
MR2B is accessed when the Channel B MR pointer points to MR2,
which occurs after any access to MR1B. Accesses to MR2B do not
change the pointer.
The bit definitions for mode register are identical to the bit
definitions for MR2A, except that all control actions apply to the
Channel B receiver and transmitter and the corresponding inputs
and outputs.
CSRA – Channel A Clock Select Register
CSRA[7:4] – Channel A Receiver Clock Select
This field selects the baud rate clock for the Channel A receiver.
The field definition is shown in Table 3.
CSRA[3:0] – Channel A Transmitter Clock Select
This field selects the baud rate clock for the Channel A transmitter.
The field definition is as shown in Table 3, except as follows:
CSRA[3:0]
ACR[7] = 0
1110
1111
IP3-1X
Baud Rate ACR[7] = 1
IP3-16X
IP3-1X
IP3-16X
The transmitter and receiver clock is always a 16X clock except
for 1111 selection
.
Table 3.
CSRA[7:4]
Baud Rate Clock = 3.6864 MHz
ACR[7] = 0
Baud Rate ACR[7] = 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
50
110
134.5
200
300
600
1,200
1,050
2,400
4,800
7,200
9,600
38.4k
Timer
IP4-16X
IP4-1X
75
110
134.5
150
300
600
1,200
2,000
2,400
4,800
1,800
9,600
19.2k
Timer
IP4-16X
IP4-1X
See Table 6
.
CSRB – Channel B Clock Select Register
CSRB[7:4] – Channel B Receiver Clock Select
This field selects the baud rate clock for the Channel B receiver.
The field definition is as shown in Table 3, except as follows:
CSRB[7:4]
ACR[7] = 0
Baud Rate ACR[7] = 1
1110
1111
IP2-16X
IP2-1X
IP2-16X
IP2-1X
The receiver clock is always a 16X clock except for CSRB[7:4] =
1111.
CSRB[3:0] – Channel B Transmitter Clock Select
This field selects the baud rate clock for the Channel B transmitter.
The field definition is as shown in Table 3, except as follows:
CSRB[3:0]
ACR[7] = 0
Baud Rate ACR[7] = 1
1110
1111
IP5-16X
IP5-1X
IP5-16X
IP5-1X
The transmitter clock is always a 16X clock except for CSRB[3:0] =
1111.
CRA – Channel A Command Register
CRA is a register used to supply commands to Channel A. Multiple
commands can be specified in a single write to CRA as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
CRA[7] – Not Used
Should be set to zero for upward compatibility with newer parts.
CRA[6:4] – Miscellaneous Commands
The encoded value of this field may be used to specify a single
command as follows:
CRA[6:4] – COMMAND
NOTE: Access to the upper four bits of the command register should be separated by three
(3) edges of the X1 clock.
000
No command.
001
Reset MR pointer. Causes the Channel A MR pointer to point to MR1.
010
Reset receiver. Resets the Channel A receiver as if a hardware reset had been ap-
plied. The receiver is disabled and the FIFO is flushed.
011
Reset transmitter. Resets the Channel A transmitter as f a hardware reset had been
applied.
100
Reset error status. Clears the Channel A Received Break, Parity Error, and Overrun
Error bits n the status register (SRA[7:4]). Used n character mode to clear OE status
(although RB, PE and FE bits will also be cleared) and n block mode to clear all error
status after a block of data has been received.
101
Reset Channel A break change interrupt. Causes the Channel A break detect
change bit in the interrupt status register (ISR[2]) to be cleared to zero.
110
Start break. Forces the TxDA output Low (spacing). If the transmitter is empty the
start of the break condition will be delayed up to two bit times. If the transmitter is
active the break begins when transmission of the character s completed. If a charac-
ter s n the THR, the start of the break will be delayed until that character, or any other
loaded subsequently are transmitted. The transmitter must be enabled for this com-
mand to be accepted.
111
Stop break. The TxDA line will go High (marking) within two bit times. TxDA will
remain High for one bit time before the next character, if any, is transmitted.
CRA[3] – Disable Channel A Transmitter
This command terminates transmitter operation and reset the
TxDRY and TxEMT status bits. However, if a character is being
transmitted or if a character is in the THR when the transmitter is
disabled, the transmission of the character(s) is completed before
assuming the inactive state.
CRA[2] – Enable Channel A Transmitter
Enables operation of the Channel A transmitter. The TxRDY status
bit will be asserted.
CRA[1] – Disable Channel A Receiver
This command terminates operation of the receiver immediately – a
character being received will be lost. The command has no effect
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