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參數(shù)資料
| 型號(hào)： | SD-14531D3-205 |
| 廠商： | DATA DEVICE CORP |
| 元件分類(lèi)： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PDIP36 |
| 封裝： | KOVER, DDIP-36 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 272K |
| 代理商： | SD-14531D3-205 |
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ProASIC3/E Flash Family FPGAs
v2.1
2-1
Device Architecture
Introduction
Flash Technology
Advanced Flash Switch
Unlike SRAM FPGAs, the ProASIC3 family uses a live at
power-up ISP Flash switch as its programming element.
Flash cells are distributed throughout the device to
provide nonvolatile, reconfigurable programming to
connect signal lines to the appropriate VersaTile inputs
and outputs. In the Flash switch, two transistors share
the floating gate, which stores the programming
information (Figure 2-1). One is the sensing transistor,
which is only used for writing and verification of the
floating gate voltage. The other is the switching
transistor. The latter is used to connect or separate
routing nets, or to configure VersaTile logic. It is also
used to erase the floating gate. Dedicated high-
performance lines are connected as required using the
Flash switch for fast, low-skew, global signal distribution
throughout the device core. Maximum core utilization is
possible for virtually any design. The use of the Flash
switch technology also removes the possibility of firm
errors, which are increasingly common in SRAM-based
FPGAs.
Figure 2-1 ProASIC3 Flash-Based Switch
Sensing
Switching
Switch In
Switch Out
Word
Floating Gate
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SD-14531F1-204 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
| SD-14531F2-202 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
| SD-14531F3-204 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
| SD-14531F1-802 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| SD-14531F1-804 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
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